A documentation of my learning journey through the RISC-V MYTH (Microprocessor for You in Thirty Hours) Program, where I explored RISC-V architecture, digital design using TL-Verilog, and implemented a pipelined RISC-V processor in Makerchip.
During this workshop, I progressed from understanding RISC-V software execution to implementing and verifying a pipelined RISC-V CPU.
Key topics covered:
- RISC-V ISA Fundamentals
- GNU Toolchain & Assembly Programming
- ABI & Verification Flow
- Digital Logic Design
- TL-Verilog & Makerchip
- CPU Microarchitecture
- Pipelining & Hazard Handling
- Processor Verification
| Day | Topics | Documentation |
|---|---|---|
| Day 01 | RISC-V ISA, GNU Toolchain, Number Systems | Day 01 |
| Day 02 | ABI & Verification Flow | Day 02 |
| Day 03 | Combinational & Sequential Logic using TL-Verilog | Day 03 |
| Day 04 | RISC-V CPU Microarchitecture | Day 04 |
| Day 05 | Pipelining, Hazards & Complete CPU Design | Day 05 |
The final project was the implementation of a pipelined RISC-V processor using TL-Verilog and Makerchip.
Project Name: VJ_RISCV_Pipelined_Core_v1
Sandbox Link: (https://myth.makerchip.com/v140/ide/~068fohN7/p-0RghrL)
- RISC-V ISA
- Assembly Programming
- ABI Concepts
- TL-Verilog
- Makerchip
- CPU Datapath Design
- Pipelining
- Hazard Handling
- Verification & Debugging
- RTL Design Fundamentals
Special thanks to:
- Kunal Ghosh
- Steve Hoover
- Shrihari
- VSD Team
- Redwood EDA
- Makerchip Team
for providing the resources and guidance throughout the RISC-V MYTH Program.
Vijay Kumar
ECE Student | VLSI Enthusiast | RTL Design Learner
LinkedIn: https://www.linkedin.com/in/vijay-kumar-b9a9bb271
GitHub: https://github.com/vijay080604