RISC-V: Open-source instruction set architecture based on reduced instruction set computer principles.
A Reconfigurable RISC-V Core for Approximate Computing
This is an HTML/Javascript CPU simulator and assembler for the CPU I designed. Originally, I created this CPU on paper many years ago for a homework assignment in college. More recently, I implemented my design in the Logisim logic simulator, and eventually it ran on an FPGA.
A platform for learning and experimenting with logic circuits
Project implementations for the NAND2Tetris (Elements of Computing Systems) course, building a complete computer system from NAND gates to a functional CPU using HDL and low-level system design.
Reusable 4-bit CPU in Logisim with Verilog HDL, ISA docs, and a browser playground
Computer Architecture UIUC SP 2018
Design of Banked Memory Access Unit for Load Store Instructions of a 32-bit Vector Processor
In this project, you will be tasked with implementing pipeline registers and connecting all the modules you've created so far to build a complete RISC-V processor. The successful completion of this project will result in a functional MIPS processor, and you'll have the opportunity to gain bonus points by handling hazards.
Verilog implementation of 8-bit CISC Processor using 4 phase clocking scheme
These are various files pertaining to a CPU I designed. Can be used in conjunction with my Logisim CPU youtube video series.
A custom 32-bit RISC processor implemented in Verilog, demonstrating datapath, control logic, and instruction execution.
Aggreage of my past CPU designs.
This repository contains my work in completing the course titled "Building a RISC-V CPU Core" offered by the Linux Foundation through edX.
Sample Verilog codes for digital circuits
The purpose of this project is to design, simulate, implement, and verify a simpleRISC Computer (Mini SRC) consisting of a simple RISC processor, memory, and I/O.
FISC - Flexible Instruction Set Computer - Is the new Instruction Set Architecture inspired by ARMv8 and x86-64
Implementation of a simple 5-stage 32-bit pipelined processor and its assembler using VHDL and Python
Turing-Complete 8-bit CPU from 12K+ Logic Gates: Asymmetric 10-bit Addressing & 16-Level Call Stack with Full Toolchain – Solo Built by a 12-Year-Old in 12 days
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