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degital-design

Here are 6 public repositories matching this topic...

bjwanneng / veriflow-cc

VeriFlow-CC: A Claude Code-driven RTL design pipeline. Automates Chip-on-Chat from architecture to synthesis (iVerilog/Yosys) using a stateful, zero-dependency LLM orchestration skill. Features sub-agent nesting for code gen and behavioral-driven verification.

digital verilog hdl yosys iverilog ai-agents rtl-design chip-design llm-agents eda-automator degital-design claude-code-skills claude-code-skill

Updated Apr 20, 2026
Verilog

Abdelrahman1810 / RTL-Verification-of-AMBA3_4-APB-Protocol

This repository contains the digital design and verification of the AMBA3 (Advanced Microcontroller Bus Architecture) and AMBA4 APB (Advanced Peripheral Bus) protocols.

tcl verilog systemverilog questasim questa verfication degital-design

Updated Aug 26, 2024
SystemVerilog

rogerhao66666 / I2C-controller

i2c rtl verilog i2c-bus degital-design

Updated Jul 23, 2024
Verilog

RjSarkar83 / Brand_Designer

Ranjan Sarkar – Visual Brand Designer 2025

art graphics vector advertisement illustration branding designing-design digital-business-card degital-design

Updated Mar 12, 2026
HTML

khaled759 / UART

UART VHDL code with programmable baud rate

fpga communication-protocol vhdl-code degital-design

Updated Jul 16, 2025
VHDL

mrchowdhury880-commits / New-resposltory-

Index.Html

css html website potfolio degital-design

Updated Oct 5, 2025

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