ASIC implementation flow infrastructure, successor to OpenLane

JSilicon: A dual-mode 8-bit CPU core designed entirely from scratch by an AI major during mandatory military service in South Korea. This open-source Verilog project proves that real silicon design — from ALU to CPU architecture — is possible even under the most extreme constraints.

Parametric layout generator for digital, analog and mixed-signal integrated circuits

open source hardware synthesis. SystemVerilog, VHDL and ABEL-HDL to gate-level netlists

Submission template for Tiny Tapeout IHP shuttles - Verilog HDL Projects

Skywater 130nm Klayout Device Generators PDK

This repository contain the implementaton of RV32I 5-Stage-Pipeline-Processor based on RISC-V ISA and designed on Verilog

Open NPU is an open-source project dedicated to creating a flexible, extensible, and high-performance neural processing unit (NPU) architecture. Open NPU aims to democratize access to cutting-edge neural processing technology for machine learning and AI applications.

Advanced Physical Design Using OpenLANE/SKY130 course notes by Ojasvi Shah

This project is focused on the design and verification of digital logic circuits, particularly targeting chip design using Verilog, SystemVerilog, and SVA. The main objectives included designing modules compliant with industry standards such as APB (Advanced Peripheral Bus), memory systems, and systolic matrix multiplication.

Conda + KLayout

Hack4Her: Logic Synthesis for AI

GDSII/OASIS layouts, including fractals, generated in working Google Colab notebooks. Layout previews are plotted as 2D graphics before exporting.

xspcomm encapsulates the DPI-based digital circuit and provides various high-level language operation interfaces.

Model Context Protocol (MCP) server for OpenROAD

Multi-agent RISC-V verification and test-generation framework for AI-assisted RTL, ISS, compliance, coverage, and debug workflows.

The Voyager flight computer on SKY130 silicon. 58 cells. Currently 24 billion km away.

VeriFlow-CC: A Claude Code-driven RTL design pipeline. Automates Chip-on-Chat from architecture to synthesis (iVerilog/Yosys) using a stateful, zero-dependency LLM orchestration skill. Features sub-agent nesting for code gen and behavioral-driven verification.

Carleton University / ELEC4609 Integrated Circuit Design and Fabrication / Project: Static Logic PRSG (Pseudo Random Sequence Generator) chip design, fabrication and testing.

A curated list of surveys, reviews, and awesome lists on the application of Large Language Models (LLMs) and AI for Electronic Design Automation (EDA) and chip design.