Yell/refactor config

.github/workflows/ci.yml

@@ -81,7 +81,7 @@ jobs:
       #   run: uv run pyright chipcompiler
 
       - name: Pytest
-        run: uv run pytest test/ --ignore=test/test_harden.py --ignore=test/test_rcx.py --cov=chipcompiler --cov-report=
+        run: uv run pytest test/ --ignore=test/test_harden.py --ignore=test/test_rcx.py --ignore=test/examples/test_soc.py --cov=chipcompiler --cov-report=
 
       - name: Publish coverage summary
         if: always()

chipcompiler/data/pdk.py

@@ -90,47 +90,32 @@ def PDK_ICS55(pdk_root: str = "") -> PDK:
         "{}/ics55_LLSC_H7CR/liberty/ics55_LLSC_H7CR_ss_rcworst_1p08_125_nldm.lib".format(stdcell_dir),
         "{}/ics55_LLSC_H7CL/liberty/ics55_LLSC_H7CL_ss_rcworst_1p08_125_nldm.lib".format(stdcell_dir)
     ]
-    mapping_file = "{}/corners/ICsprout_55LLULP_1P6M_5lc_V1p1_cell.map".format(resolved_root)
+    mapping_file = ""
     corners = [
         {
             "name" : "TYPICAL",
             "temperature" : [25],
-            "ecc_tf" : "{}/corners/TYP.json".format(resolved_root),
-            "itf_file" : "{}/corners/TYP.itf".format(resolved_root),
-            "captab_file" : "{}/corners/TYP.captab".format(resolved_root),
-            "spef_file" : "{}/corners/TYP.spef".format(resolved_root)
+            "spef_file" : "./TYP.spef"
         },
         {
             "name" : "RCbest",
             "temperature" : [-40, 125],
-            "ecc_tf" : "{}/corners/RCbest.json".format(resolved_root),
-            "itf_file" : "{}/corners/RCbest.itf".format(resolved_root),
-            "captab_file" : "{}/corners/RCbest.captab".format(resolved_root),
-            "spef_file" : "{}/corners/RCbest.spef".format(resolved_root)
+            "spef_file" : "./RCbest.spef"
         },
         {
             "name" : "RCworst",
             "temperature" : [-40, 125],
-            "ecc_tf" : "{}/corners/RCworst.json".format(resolved_root),
-            "itf_file" : "{}/corners/RCworst.itf".format(resolved_root),
-            "captab_file" : "{}/corners/RCworst.captab".format(resolved_root),
-            "spef_file" : "{}/corners/RCworst.spef".format(resolved_root)
+            "spef_file" : "./RCworst.spef"
         },
         {
             "name" : "Cbest",
             "temperature" : [-40, 125],
-            "ecc_tf" : "{}/corners/Cbest.json".format(resolved_root),
-            "itf_file" : "{}/corners/Cbest.itf".format(resolved_root),
-            "captab_file" : "{}/corners/Cbest.captab".format(resolved_root),
-            "spef_file" : "{}/corners/Cbest.spef".format(resolved_root)
+            "spef_file" : "./Cbest.spef"
         },
         {
             "name" : "Cworst",
             "temperature" : [-40, 125],
-            "ecc_tf" : "{}/corners/Cworst.json".format(resolved_root),
-            "itf_file" : "{}/corners/Cworst.itf".format(resolved_root),
-            "captab_file" : "{}/corners/Cworst.captab".format(resolved_root),
-            "spef_file" : "{}/corners/Cworst.spef".format(resolved_root)
+            "spef_file" : "./Cworst.spef"
         }
     ]
 

chipcompiler/data/workspace.py

@@ -257,12 +257,24 @@ def init_workspace_config(workspace: Workspace) -> None:
     router["RT"]["-top_routing_layer"] = workspace.parameters.data.get("Top layer", "")
     json_write(workspace.config[f"{StepEnum.ROUTING.value}"], router)
 
-    rcx = json_read(workspace.config[f"{StepEnum.RCX.value}"])
-    rcx["pdk"] = "ics55" if workspace.pdk.name == "ics55" else ""
-    rcx["mapping_file"] = workspace.pdk.mapping_file
-    corners = deepcopy(workspace.pdk.corners)
-    rcx["corners"] = corners
-    json_write(workspace.config[f"{StepEnum.RCX.value}"], rcx)
+    # rcx = json_read(workspace.config[f"{StepEnum.RCX.value}"])
+    # rcx["pdk"] = "ics55" if workspace.pdk.name == "ics55" else ""
+    # rcx["mapping_file"] = workspace.pdk.mapping_file
+    # corners = deepcopy(workspace.pdk.corners)
+    # rcx["corners"] = corners
+    # json_write(workspace.config[f"{StepEnum.RCX.value}"], rcx)
+
+    sta = json_read(workspace.config[f"{StepEnum.STA.value}"])
+    pdk_root = workspace.pdk.root.rstrip(os.sep)
+    for liberty in sta.get("liberty", []):
+        liberty["path"] = [
+            path
+            if path == pdk_root or path.startswith(f"{pdk_root}{os.sep}")
+            else os.path.join(workspace.pdk.root, path.lstrip(os.sep))
+            for path in liberty.get("path", [])
+        ]
+
+    json_write(workspace.config[f"{StepEnum.STA.value}"], sta)
 
     dreamplace = json_read(workspace.config["dreamplace"])
     dreamplace["lef_input"] = [workspace.pdk.tech, *workspace.pdk.lefs]
@@ -613,6 +625,15 @@ def load_workspace(directory : str) -> Workspace:
     if len(spef_path) > 0:
         pdk.spef = spef_path[0]
 
+    # update lef and lib paths based on config
+    from chipcompiler.utility import json_read
+    db_json = json_read(workspace.config.get("db", ""))
+    if db_json.get("INPUT", {}).get("tech_lef_path", "") != "":
+        pdk.tech = db_json.get("INPUT", {}).get("tech_lef_path", "")
+    if db_json.get("INPUT", {}).get("lef_paths", []) != []:
+        pdk.lefs = db_json.get("INPUT", {}).get("lef_paths", [])
+    if db_json.get("INPUT", {}).get("lib_path", []) != []:
+        pdk.libs = db_json.get("INPUT", {}).get("lib_path", [])
     workspace.pdk = pdk
 
     #update config

chipcompiler/engine/flow.py

@@ -5,16 +5,35 @@
 import time
 import logging
 import traceback
-from multiprocessing import Process
-from threading import Thread
+from threading import Event, Thread
 
 from chipcompiler.data import Workspace, WorkspaceStep, StateEnum, StepEnum, log_flow
 from chipcompiler.engine import EngineDB
-from chipcompiler.utility import track_process_memory
 from chipcompiler.utility.log import redirect_stdio_to_file
 
 logger = logging.getLogger(__name__)
 
+def get_process_rss_mb(pid : int) -> float:
+    peak_memory = 0
+    try:
+        with open(f"/proc/{pid}/status", 'r') as f:
+            for line in f:
+                if line.startswith("VmRSS:"):
+                    rss_kb = int(line.split()[1])
+                    peak_memory = rss_kb / 1024
+                    break
+    except Exception:
+        pass
+    return peak_memory
+
+def track_current_process_memory(pid : int,
+                                 stop_event : Event,
+                                 peak_memory : list[float]):
+    while not stop_event.is_set():
+        peak_memory[0] = max(peak_memory[0], get_process_rss_mb(pid))
+        stop_event.wait(0.1)
+    peak_memory[0] = max(peak_memory[0], get_process_rss_mb(pid))
+
 class EngineFlow:
     def __init__(self, workspace : Workspace, engine_db : EngineDB = None):
         self.workspace = workspace
@@ -321,17 +340,29 @@ def run_step(self,
 
         step_tag = f"{workspace_step.name}({workspace_step.tool})"
         self.workspace.logger.info(f"[STEP] {step_tag} pid={os.getpid()} started")
-
+
+        pid = os.getpid()
+        start_memory_mb = get_process_rss_mb(pid)
+        peak_memory = [start_memory_mb]
+        stop_memory_monitor = Event()
+        memory_monitor = Thread(target=track_current_process_memory,
+                                args=(pid, stop_memory_monitor, peak_memory),
+                                daemon=True)
+        memory_monitor.start()
         try:
             from chipcompiler.tools import run_step as run_tool_step
             result = run_tool_step(workspace=self.workspace, step=workspace_step, ecc_module=self.engine_db.engine)
             self.workspace.logger.info(f"[STEP] {step_tag} finished result={result}")
         except Exception:
             self.workspace.logger.error(f"[STEP] {step_tag} failed with exception")
             traceback.print_exc()
+        finally:
+            stop_memory_monitor.set()
+            memory_monitor.join()
 
         # compute metrics
-        peak_memory_mb = 0
+        peak_memory_mb = peak_memory[0] - start_memory_mb
+        peak_memory_mb = 0 if peak_memory_mb < 0 else round(peak_memory_mb, 3)
         elapsed = time.time() - start_time
         runtime = f"{int(elapsed // 3600)}:{int((elapsed % 3600) // 60)}:{int(elapsed % 60)}"
 

chipcompiler/tools/ecc/configs/rcx.json

@@ -1,62 +1,4 @@
 {
-    "pdk": "",
     "thread_num": 64,
-    "output": "/RCX_ecc/output",
-    "mapping_file": "/corners/ICsprout_55LLULP_1P6M_5lc_V1p1_cell.map",
-    "corners": [
-        {
-            "name": "TYPICAL",
-            "temperature": [25],
-            "ecc_tf": "/corners/TYP.json",
-            "itf_file": "/corners/TYP.itf",
-            "captab_file": "/corners/TYP.captab",
-            "spef_file": [
-                { "25" : "/RCX_ecc/output/gcd_TYPICAL_25C.spef" }
-            ]
-        },
-        {
-            "name": "RCbest",
-            "temperature": [-40, 125],
-            "ecc_tf": "/corners/RCbest.json",
-            "itf_file": "/corners/RCbest.itf",
-            "captab_file": "/corners/RCbest.captab",
-            "spef_file": [
-                { "-40" : "/RCX_ecc/output/gcd_RCbest_m40C.spef" },
-                { "125" : "/RCX_ecc/output/gcd_RCbest_125C.spef" }
-            ]
-        },
-        {
-            "name": "RCworst",
-            "temperature": [-40, 125],
-            "ecc_tf": "/corners/RCworst.json",
-            "itf_file": "/corners/RCworst.itf",
-            "captab_file": "/corners/RCworst.captab",
-            "spef_file": [
-                { "-40" : "/RCX_ecc/output/gcd_RCworst_m40C.spef" },
-                { "125" : "/RCX_ecc/output/gcd_RCworst_125C.spef" }
-            ]
-        },
-        {
-            "name": "Cbest",
-            "temperature": [-40, 125],
-            "ecc_tf": "/corners/Cbest.json",
-            "itf_file": "/corners/Cbest.itf",
-            "captab_file": "/corners/Cbest.captab",
-            "spef_file": [
-                { "-40" : "/RCX_ecc/output/gcd_Cbest_m40C.spef" },
-                { "125" : "/RCX_ecc/output/gcd_Cbest_125C.spef" }
-            ]
-        },
-        {
-            "name": "Cworst",
-            "temperature": [-40, 125],
-            "ecc_tf": "/corners/Cworst.json",
-            "itf_file": "/corners/Cworst.itf",
-            "captab_file": "/corners/Cworst.captab",
-            "spef_file": [
-                { "-40" : "/RCX_ecc/output/gcd_Cworst_m40C.spef" },
-                { "125" : "/RCX_ecc/output/gcd_Cworst_125C.spef" }
-            ]
-        }
-    ]
+    "output": "/RCX_ecc/output"
 }

chipcompiler/tools/ecc/configs/sta.json

@@ -5,39 +5,39 @@
             "temperature": 125,
             "path" : [
                 "/IP/STD_cell/ics55_LLSC_H7C_V1p10C100/ics55_LLSC_H7CR/liberty/ics55_LLSC_H7CR_ss_rcworst_1p08_125_nldm.lib",
-                "/IP/STD_cell/ics55_LLSC_H7C_V1p10C100/ics55_LLSC_H7CL/liberty/ics55_LLSC_H7CR_ss_rcworst_1p08_125_nldm.lib"
+                "/IP/STD_cell/ics55_LLSC_H7C_V1p10C100/ics55_LLSC_H7CL/liberty/ics55_LLSC_H7CL_ss_rcworst_1p08_125_nldm.lib"
             ]
         },
         {
             "corner": "WCL",
             "temperature": -40,
             "path" : [
                 "/IP/STD_cell/ics55_LLSC_H7C_V1p10C100/ics55_LLSC_H7CR/liberty/ics55_LLSC_H7CR_ss_cworst_1p08_m40_nldm.lib",
-                "/IP/STD_cell/ics55_LLSC_H7C_V1p10C100/ics55_LLSC_H7CL/liberty/ics55_LLSC_H7CR_ss_cworst_1p08_m40_nldm.lib"
+                "/IP/STD_cell/ics55_LLSC_H7C_V1p10C100/ics55_LLSC_H7CL/liberty/ics55_LLSC_H7CL_ss_cworst_1p08_m40_nldm.lib"
             ]
         },
         {
             "corner": "TYP",
             "temperature": 25,
             "path" : [
                 "/IP/STD_cell/ics55_LLSC_H7C_V1p10C100/ics55_LLSC_H7CR/liberty/ics55_LLSC_H7CR_typ_tt_1p2_25_nldm.lib",
-                "/IP/STD_cell/ics55_LLSC_H7C_V1p10C100/ics55_LLSC_H7CL/liberty/ics55_LLSC_H7CR_typ_tt_1p2_25_nldm.lib"
+                "/IP/STD_cell/ics55_LLSC_H7C_V1p10C100/ics55_LLSC_H7CL/liberty/ics55_LLSC_H7CL_typ_tt_1p2_25_nldm.lib"
             ]
         },
         {
             "corner": "MIN",
             "temperature": -40,
             "path" : [
                 "/IP/STD_cell/ics55_LLSC_H7C_V1p10C100/ics55_LLSC_H7CR/liberty/ics55_LLSC_H7CR_ff_rcbest_1p32_m40_nldm.lib",
-                "/IP/STD_cell/ics55_LLSC_H7C_V1p10C100/ics55_LLSC_H7CL/liberty/ics55_LLSC_H7CR_ff_rcbest_1p32_m40_nldm.lib"
+                "/IP/STD_cell/ics55_LLSC_H7C_V1p10C100/ics55_LLSC_H7CL/liberty/ics55_LLSC_H7CL_ff_rcbest_1p32_m40_nldm.lib"
             ]
         },
         {
             "corner": "ML",
             "temperature": 125,
             "path" : [
                 "/IP/STD_cell/ics55_LLSC_H7C_V1p10C100/ics55_LLSC_H7CR/liberty/ics55_LLSC_H7CR_ff_cbest_1p32_125_nldm.lib",
-                "/IP/STD_cell/ics55_LLSC_H7C_V1p10C100/ics55_LLSC_H7CL/liberty/ics55_LLSC_H7CR_ff_cbest_1p32_125_nldm.lib"
+                "/IP/STD_cell/ics55_LLSC_H7C_V1p10C100/ics55_LLSC_H7CL/liberty/ics55_LLSC_H7CL_ff_cbest_1p32_125_nldm.lib"
             ]
         }
     ],