ECOS Chip Compiler (ECC)

Open-Source Chip Design Automation Solution

Overview

ECOS Chip Compiler is an open-source chip design automation solution that integrates EDA tools (Yosys, ECC-Tools, KLayout) to achieve complete RTL-to-GDS design flow. Developed and maintained by the ECOS Team.

The GUI (ECOS Studio) has been moved to the ecos-studio repo.

How to use:

• CLI (ecc) - Project-oriented command-line flow execution
• Python API - Use chipcompiler as a library

Quick Start

CLI Flow Runner

Use nix run .#cli -- ... to create an ECC project, validate its ecc.toml, and run the full RTL2GDS flow.

nix run .#cli -- init gcd
cp ./rtl/gcd.v gcd/rtl/gcd.v

Edit gcd/ecc.toml:

[design]
name = "gcd"
top = "gcd"
rtl = ["rtl/gcd.v"]
clock_port = "clk"
frequency_mhz = 100.0

[pdk]
name = "ics55"
root = "/path/to/ics55"

[flow]
preset = "rtl2gds"
run = "default"

Then validate and run:

nix run .#cli -- check --project gcd
nix run .#cli -- run --project gcd
nix run .#cli -- status --project gcd
nix run .#cli -- metrics --project gcd
nix run .#cli -- log --project gcd

Features

• Complete RTL-to-GDS Flow - Synthesis, placement, routing, timing optimization
• Open-Source EDA Integration - Yosys (synthesis), ECC-Tools (P&R), KLayout (viewer)
• CLI Automation - Scriptable flow execution from command line
• Portable Deployment - Nix or standalone builds

🛠️ Integrated Tools

Tool	Purpose	Status
Yosys	RTL Synthesis	✅
ECC-Tools	Physical Design (P&R)	✅
KLayout	Layout Viewer	🚧

Documentation

• Documentation Index - Complete navigation
• Architecture - System design and patterns
• Development Guide - Setup and workflows
• Examples - Usage examples

Contributing

Contributions welcome! See Development Guide for setup instructions.

Acknowledgments

Special thanks to these open-source projects:

• Yosys - RTL Synthesis
• ECC-Tools - Physical Design Backend
• KLayout - Layout Viewer
• nixpkgs - A collection of Nix packages

Built by the ECOS Team

Report Issues · Discussions