Add support for Hygon Platform QoS features by shenxiaochen · Pull Request #300 · intel/intel-cmt-cat

shenxiaochen · 2025-11-20T04:21:05Z

Add support for Hygon Platform QoS features

Description

Hygon CPUs support Platform QoS features (PQoS Version V1.0) described
in the AMD Platform QoS specification.

The changes add Platform QoS features support for Hygon CPUs.

Affected parts

library
pqos utility
rdtset utility
other: (please specify)

Motivation and Context

Add Platform QoS features support for Hygon CPUs.

Hygon CPUs support Platform QoS features (PQoS Version V1.0) described
in the AMD Platform QoS specification [1].

Following Platform QoS sub-features are available on Hygon CPUs if the
underlying hardware supports it:

L3 Cache Occupancy Monitoring (CMT)
L3 External Memory Bandwidth Monitoring (MBM)
L3 Cache Allocation Enforcement (CAT)
Code and Data Prioritization (CDP)
Memory Bandwidth Enforcement/Allocation (MBA)

[1] AMD Platform QoS Extensions, Rev 1.03:
https://www.amd.com/content/dam/amd/en/documents/processor-tech-docs/other/56375_1_03_PUB.pdf

How Has This Been Tested?

Passed all tests in intel-cmt-cat/unit-test on Hygon platforms.
Run most pqos tests described below on Hygon platforms:
https://github.com/intel/intel-cmt-cat/wiki/Usage-Examples

Types of changes

Bug fix (non-breaking change which fixes an issue)
New feature (non-breaking change which adds functionality)
Breaking change (fix or feature that would cause existing functionality to not work as expected)

Checklist:

My code follows the code style of this project.
My change requires a change to the documentation.
I have updated the documentation accordingly.

ajherdri · 2025-11-21T16:13:23Z

Hi Xiaochen,
Thanks for the contribution! We are reviewing and will get back to you soon.
Thanks,
~Andrew

shenxiaochen · 2025-11-24T09:03:32Z

Hi Xiaochen, Thanks for the contribution! We are reviewing and will get back to you soon. Thanks, ~Andrew

Hi Andrew,
My honor to contribute to this project again! Thank you and the team for helping review this PR.

Note: Please help review #299 as well. The code base of this PR is on top of #299 which is a trivial bug fixing.

Best regards,
Xiaochen

Copilot

Pull request overview

This PR adds Platform QoS (Quality of Service) feature support for Hygon CPUs, which implement AMD's PQoS specification v1.0. The changes enable the intel-cmt-cat library and utilities to recognize and handle Hygon processors alongside Intel and AMD processors.

Key changes:

Introduces a new vendor identifier PQOS_VENDOR_HYGON throughout the codebase
Updates vendor detection logic to identify Hygon CPUs via CPUID signature
Extends AMD-specific code paths to include Hygon, as Hygon follows AMD's PQoS specification
Implements Hygon-specific counter length handling for monitoring capabilities

Reviewed changes

Copilot reviewed 9 out of 9 changed files in this pull request and generated 3 comments.

Show a summary per file

File	Description
lib/pqos.h	Adds PQOS_VENDOR_HYGON enum value and updates API documentation
lib/cpuinfo.c	Implements Hygon CPU detection and configuration initialization
lib/hw_cap.c	Adds Hygon-specific handling for monitoring counter length
lib/cap.c	Routes Hygon CPUs to AMD discovery functions for MBA capability
lib/api.c	Assigns AMD-specific MBA functions for Hygon vendor
lib/python/pqos/native_struct.py	Adds Python binding for PQOS_VENDOR_HYGON constant
lib/python/pqos/cpuinfo.py	Adds "HYGON" string mapping for vendor identification
pqos/alloc.c	Updates display logic to use AMD-style naming for Hygon
rdtset/rdt.c	Extends AMD-specific MBA and display logic to include Hygon

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rkanagar · 2026-01-26T11:32:34Z

Hi @shenxiaochen ,
Rebase this PR. I will merge this.

Thanks,
Raghavan K.

shenxiaochen · 2026-01-26T15:36:01Z

Hi @shenxiaochen , Rebase this PR. I will merge this.

Thanks, Raghavan K.

@rkanagar Thank you very much for help!
There is a conflict with commit 0dafb6e ("lib: added IORDT CAT from RDT specification 1.1"). I will try to address the conflict and then rebase this PR.

shenxiaochen · 2026-01-26T16:14:22Z

@rkanagar The conflict is resolved. This PR is rebased. Please help review and merge. Thank you!

shenxiaochen · 2026-01-26T17:11:23Z

Hi @shenxiaochen , Rebase this PR. I will merge this.

Thanks, Raghavan K.

@rkanagar

Please hold on to merge this PR. I need to run more tests.
Actually I found some regressions after rebase on top of master tree. These issues never occurred prior to the rebase on Hygon platforms.

Are they related to commit 0dafb6e ("lib: added IORDT CAT from RDT specification 1.1")?

Could you help double check if these commands work on top of master tree on Intel platforms? Thank you!
(Resctrl filesystem is mounted successfully on /sys/fs/resctrl and all RDT/Platform QoS features work well)
(1) $ pqos -s --iface=os
Unexpected output on Hygon platform, it looks like:

L3CA/MBA COS definitions for Socket 0:
    L3CA COS0 => DATA 0x0, CODE 0x7f60e310b47d

But $pqos -s --iface=msr works well on Hygon platform.

(2) pqos --iface=os -e issue:
$ pqos --iface=os -e "llc:1=0x000f;llc:2=0x0ff0;"

NOTE:  Mixed use of MSR and kernel interfaces to manage
       CAT or CMT & MBM may lead to unexpected behavior.
WARN: Could not obtain ERDT table
ERROR: Invalid file arguments!
Core Complex0 L3CA COS1 - FAILED!
Allocation configuration error!

But $ pqos --iface=msr -e "llc:1=0x000f;llc:2=0x0ff0;" works well on Hygon platform.

(3) unit-test failures:

$ cd unit-test
$ make && make run

Unexpected failure on Hygon platform. It looks like:

grep FAIL make_run_master.log
[  FAILED  ] test_pqos_mba_set_init
[  FAILED  ] 1 test(s), listed below:
[  FAILED  ] test_pqos_mba_set_init
 1 FAILED TEST(S)
[  FAILED  ] test_pqos_l3ca_set_param
[  FAILED  ] test_pqos_mba_set_param
[  FAILED  ] 2 test(s), listed below:
[  FAILED  ] test_pqos_l3ca_set_param
[  FAILED  ] test_pqos_mba_set_param
 2 FAILED TEST(S)
[  FAILED  ] test_pqos_mba_set_hw
[  FAILED  ] 1 test(s), listed below:
[  FAILED  ] test_pqos_mba_set_hw
 1 FAILED TEST(S)
...
...

rkanagar · 2026-01-26T18:28:07Z

Hi @shenxiaochen , Rebase this PR. I will merge this.
Thanks, Raghavan K.

@rkanagar

Please hold on to merge this PR. I need to run more tests. Actually I found some regressions after rebase on top of master tree. These issues never occurred prior to the rebase on Hygon platforms.

Are they related to commit 0dafb6e ("lib: added IORDT CAT from RDT specification 1.1")?

Could you help double check if these commands work on top of master tree on Intel platforms? Thank you! (Resctrl filesystem is mounted successfully on /sys/fs/resctrl and all RDT/Platform QoS features work well) (1) $ pqos -s --iface=os Unexpected output on Hygon platform, it looks like:
L3CA/MBA COS definitions for Socket 0:
    L3CA COS0 => DATA 0x0, CODE 0x7f60e310b47d
But $pqos -s --iface=msr works well on Hygon platform.

(2) pqos --iface=os -e issue: $ pqos --iface=os -e "llc:1=0x000f;llc:2=0x0ff0;"
NOTE:  Mixed use of MSR and kernel interfaces to manage
       CAT or CMT & MBM may lead to unexpected behavior.
WARN: Could not obtain ERDT table
ERROR: Invalid file arguments!
Core Complex0 L3CA COS1 - FAILED!
Allocation configuration error!
But $ pqos --iface=msr -e "llc:1=0x000f;llc:2=0x0ff0;" works well on Hygon platform.

(3) unit-test failures:
$ cd unit-test
$ make && make run
Unexpected failure on Hygon platform. It looks like:
grep FAIL make_run_master.log
[  FAILED  ] test_pqos_mba_set_init
[  FAILED  ] 1 test(s), listed below:
[  FAILED  ] test_pqos_mba_set_init
 1 FAILED TEST(S)
[  FAILED  ] test_pqos_l3ca_set_param
[  FAILED  ] test_pqos_mba_set_param
[  FAILED  ] 2 test(s), listed below:
[  FAILED  ] test_pqos_l3ca_set_param
[  FAILED  ] test_pqos_mba_set_param
 2 FAILED TEST(S)
[  FAILED  ] test_pqos_mba_set_hw
[  FAILED  ] 1 test(s), listed below:
[  FAILED  ] test_pqos_mba_set_hw
 1 FAILED TEST(S)
...
...

Hi @shenxiaochen ,
OK We will wait. We are working in Unit-test cases also. We will merge our fixes in this week.

Yes it works fine
#pqos --iface=os -e "llc:1=0x000f;llc:2=0x0ff0;"
NOTE: Mixed use of MSR and kernel interfaces to manage
CAT or CMT & MBM may lead to unexpected behavior.
WARN: Could not obtain ERDT table
SOCKET0 L3CA COS1 => MASK 0xf
SOCKET1 L3CA COS1 => MASK 0xf
SOCKET0 L3CA COS2 => MASK 0xff0
SOCKET1 L3CA COS2 => MASK 0xff0
Allocation configuration altered.

Thanks,
Raghavan K.

shenxiaochen · 2026-01-27T06:41:15Z

Rebased to resolve the space char issue mentioned in #300 (review)

shenxiaochen · 2026-01-27T07:41:04Z

Hi @shenxiaochen , OK We will wait. We are working in Unit-test cases also. We will merge our fixes in this week.

@rkanagar
Hi Raghavan,
Thank you for your information. I'll skip the Unit-test until the related fixes are merged.

Yes it works fine #pqos --iface=os -e "llc:1=0x000f;llc:2=0x0ff0;" NOTE: Mixed use of MSR and kernel interfaces to manage CAT or CMT & MBM may lead to unexpected behavior. WARN: Could not obtain ERDT table SOCKET0 L3CA COS1 => MASK 0xf SOCKET1 L3CA COS1 => MASK 0xf SOCKET0 L3CA COS2 => MASK 0xff0 SOCKET1 L3CA COS2 => MASK 0xff0 Allocation configuration altered.

Thanks, Raghavan K.

Please ignore these two issues, which resulted from testing in an unclean chaos environment. I can confirm they do not occur in a clean setup on Hygon platforms.

(1) $ pqos -s --iface=os
(2) $ pqos --iface=os -e "llc:1=0x000f;llc:2=0x0ff0;"

Could you please review and merge this PR at your convenience?
Thank you very much!

Best regards,
Xiaochen

Hygon CPUs support Platform QoS features (PQoS Version V1.0) described in the AMD Platform QoS specification[1]. Following Platform QoS sub-features are available on Hygon CPUs if the underlying hardware supports it: - L3 Cache Occupancy Monitoring (CMT) - L3 External Memory Bandwidth Monitoring (MBM) - L3 Cache Allocation Enforcement (CAT) - Code and Data Prioritization (CDP) - Memory Bandwidth Enforcement/Allocation (MBA) [1] AMD Platform QoS Extensions, Rev 1.03: https://www.amd.com/content/dam/amd/en/documents/processor-tech-docs/other/56375_1_03_PUB.pdf Signed-off-by: Xiaochen Shen <shenxiaochen@open-hieco.net>

The default base MBM counter length (width) is 24 bits. Currently, Hygon CPU does not support the CPUID 0xF.[ECX=1]:EAX to adjust the counter length. But the Hygon CPU supports wider counter with the fixed width of 32 bits. Set the default MBM counter length to 32 bit by adjusting the offset to 8 bits for Hygon. Hygon future products will implement CPUID 0xF.[ECX=1]:EAX. Signed-off-by: Xiaochen Shen <shenxiaochen@open-hieco.net>

shenxiaochen · 2026-01-28T03:30:41Z

@rkanagar Git pushed code to fix the coding style issue mentioned in #300 (review). Thank you!

rkanagar · 2026-01-28T12:35:13Z

Merged by
4686fe1
4988de4

shenxiaochen · 2026-01-28T16:21:36Z

Merged by 4686fe1 4988de4

@rkanagar Thank you very much for help!

shenxiaochen mentioned this pull request Nov 24, 2025

Fix some Non-Contiguous CBM capability detection issues on Intel, AMD and Hygon platforms #302

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rkanagar requested a review from Copilot December 12, 2025 10:17

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Comment thread lib/pqos.h

Comment thread lib/hw_cap.c

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This was referenced Dec 30, 2025

Fix SNC state detection on non-SNC-capable platforms #304

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Show L3CA/MBA COS definitions per L3 cluster on AMD and Hygon #305

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rkanagar reviewed Jan 26, 2026

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Comment thread lib/python/pqos/cpuinfo.py Outdated

Comment thread lib/python/pqos/native_struct.py Outdated

shenxiaochen force-pushed the hygon-pqos branch from b981133 to d579891 Compare January 26, 2026 15:47

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Comment thread pqos/alloc.c Outdated

shenxiaochen force-pushed the hygon-pqos branch from d579891 to 9ab2648 Compare January 27, 2026 06:35

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Comment thread rdtset/rdt.c Outdated

shenxiaochen added 2 commits January 28, 2026 10:46

shenxiaochen force-pushed the hygon-pqos branch from 9ab2648 to 81d71ad Compare January 28, 2026 03:28

rkanagar closed this Jan 28, 2026

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shenxiaochen commented Nov 20, 2025

Description

Affected parts

Motivation and Context

How Has This Been Tested?

Types of changes

Checklist:

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