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Fix some Non-Contiguous CBM capability detection issues on Intel, AMD and Hygon platforms#302

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Fix some Non-Contiguous CBM capability detection issues on Intel, AMD and Hygon platforms#302
shenxiaochen wants to merge 3 commits intointel:masterfrom
shenxiaochen:fix-non-contiguous-cbm

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@shenxiaochen shenxiaochen commented Nov 24, 2025

Fix some Non-Contiguous CBM capability detection issues on Intel, AMD and Hygon platforms

Description

Fix three issues of L3/L2 cache Non-Contiguous CBM capability detection on Intel, AMD and Hygon platforms:
(1) lib: Fix L3 cache Non-Contiguous CBM capability with MSR interface for AMD and Hygon (for AMD and Hygon)
(2) lib: Add L3 cache Non-Contiguous CBM capability detection with OS interface (for Intel, AMD, and Hygon)
(3) lib: Add L2 cache Non-Contiguous CBM capability detection with OS interface (for Intel)

Affected parts

  • library
  • pqos utility
  • rdtset utility
  • other: (please specify)

Motivation and Context

Fix three issues of L3/L2 cache Non-Contiguous CBM capability detection on Intel, AMD and Hygon platforms.
Detect and display the correct L3/L2 cache Non-Contiguous CBM capabilities.

How Has This Been Tested?

(1) Passed "pqos -d" test:

$ pqos --iface msr -d | grep "Non-Contiguous CBM"
                Non-Contiguous CBM: unsupported/supported

$ pqos --iface os -d | grep "Non-Contiguous CBM"
                Non-Contiguous CBM: unsupported/supported

(2) Passed all tests in intel-cmt-cat/unit-test.

Types of changes

  • Bug fix (non-breaking change which fixes an issue)
  • New feature (non-breaking change which adds functionality)
  • Breaking change (fix or feature that would cause existing functionality to not work as expected)

Checklist:

  • My code follows the code style of this project.
  • My change requires a change to the documentation.
  • I have updated the documentation accordingly.

@shenxiaochen
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shenxiaochen commented Nov 24, 2025

Note: The code base of this PR is on top of #300 and #299

[This PR - #302 ]
c5c2c0c lib: Add L2 cache Non-Contiguous CBM capability detection with OS interface
2f6eb17 lib: Add L3 cache Non-Contiguous CBM capability detection with OS interface
5c54433 lib: Fix L3 cache Non-Contiguous CBM capability with MSR interface for AMD and Hygon

[PR #300 ]
b981133 lib: Set fixed MBM counter length for Hygon
90c603e lib/python: Add support for Hygon Platform QoS features
c5cc545 lib: Add support for Hygon Platform QoS features

[PR #299 ]
6a4d764 lib: Fix incorrect bitmask for MBM counter length

Best regards,
Xiaochen

@shenxiaochen shenxiaochen force-pushed the fix-non-contiguous-cbm branch 3 times, most recently from b0c93d3 to c5c2c0c Compare November 24, 2025 15:09
@ajherdri
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Hi Xiaochen,
Thanks for the contribution, we will review and get back to you soon.
This may take a week or so given the US holiday this week.
Thanks,
~Andrew

@rkanagar rkanagar requested a review from Copilot December 12, 2025 10:16
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Pull request overview

This PR fixes Non-Contiguous Cache Bit Mask (CBM) capability detection issues for Intel, AMD, and Hygon platforms. The changes add proper support for Hygon vendor detection and ensure correct L3/L2 cache Non-Contiguous CBM capability reporting across all three vendors through both MSR and OS interfaces.

Key changes:

  • Adds PQOS_VENDOR_HYGON enum value and vendor detection logic
  • Fixes L3 cache Non-Contiguous CBM capability detection for AMD and Hygon via MSR interface
  • Adds L3/L2 cache Non-Contiguous CBM capability detection via OS interface (sparse_masks)

Reviewed changes

Copilot reviewed 10 out of 10 changed files in this pull request and generated 4 comments.

Show a summary per file
File Description
lib/pqos.h Adds PQOS_VENDOR_HYGON enum value and updates documentation
lib/cpuinfo.c Adds Hygon vendor detection and configuration initialization
lib/hw_cap.c Fixes L3 Non-Contiguous CBM detection for AMD/Hygon and Hygon counter length handling
lib/os_cap.c Adds sparse_masks file reading for L3/L2 Non-Contiguous CBM detection via OS interface
lib/cap.c Routes MBA discovery to AMD path for Hygon vendor
lib/api.c Routes MBA get/set operations to AMD implementations for Hygon
rdtset/rdt.c Adds Hygon vendor checks for MBA max values and package naming
pqos/alloc.c Adds Hygon vendor checks for package naming and units
lib/python/pqos/native_struct.py Adds PQOS_VENDOR_HYGON Python constant
lib/python/pqos/cpuinfo.py Adds Hygon vendor string mapping

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Comment thread lib/hw_cap.c
Comment thread lib/os_cap.c
Comment thread lib/os_cap.c
Comment thread lib/hw_cap.c
@rkanagar
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Hi @shenxiaochen ,
First we will merge PR 300. And rebase this PR and resubmit. We will merge.
#300

Thanks,
Raghavan K.

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Hi @shenxiaochen , First we will merge PR 300. And rebase this PR and resubmit. We will merge. #300

Thanks, Raghavan K.

@rkanagar Thank you very much for help!
I will rebase this PR when PR #300 is merged.

@shenxiaochen shenxiaochen force-pushed the fix-non-contiguous-cbm branch 2 times, most recently from d1e245d to 267da84 Compare January 28, 2026 05:35
@rkanagar
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Hi @shenxiaochen ,

Please rebase this PR. We are ready to merge.

Thanks,
Raghavan K.

@shenxiaochen shenxiaochen force-pushed the fix-non-contiguous-cbm branch from 267da84 to 67f9e39 Compare January 28, 2026 16:24
@shenxiaochen
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Hi @shenxiaochen ,

Please rebase this PR. We are ready to merge.

Thanks, Raghavan K.

@rkanagar

Rebased on top of master tree (after PR #300 merged). Thank you!

Comment thread lib/hw_cap.c Outdated
@shenxiaochen shenxiaochen force-pushed the fix-non-contiguous-cbm branch from 67f9e39 to 82762b6 Compare January 29, 2026 05:04
@shenxiaochen
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@rkanagar
Git pushed code to fix the coding style issue mentioned in #302 (review)
Thank you.

Comment thread lib/hw_cap.c Outdated
…r AMD and Hygon

From Intel RDT spec[1] and AMD Platform QoS spec[2]:
The Non-Contiguous CBM support bit (CPUID.0x10.1:ECX[3]) is Intel
platform specific.

AMD and Hygon platforms support L3 cache Non-Contiguous CBM, but the
Non-Contiguous CBM support bit (CPUID.0x10.1:ECX[3]) is unused.

Currently, the capability of L3 cache Non-Contiguous CBM is incorrectly
initialized with MSR interface (--iface msr) on AMD and Hygon platforms:

$ pqos --iface msr -d | grep "Non-Contiguous CBM"
                Non-Contiguous CBM: unsupported

Fix it by setting L3 cache Non-Contiguous CBM supported for AMD and
Hygon platforms.

After fix:
$ pqos --iface msr -d | grep "Non-Contiguous CBM"
                Non-Contiguous CBM: supported

[1] Intel Architectures SDM, Vol.3B, 19.19 Intel RDT Allocation:
https://cdrdv2.intel.com/v1/dl/getContent/671200

[2] AMD Platform QoS Extensions, Rev 1.03:
https://www.amd.com/content/dam/amd/en/documents/processor-tech-docs/other/56375_1_03_PUB.pdf

Fixes: 0a1dc08 ("Non-Contiguous CBM support")
Signed-off-by: Xiaochen Shen <shenxiaochen@open-hieco.net>
…erface

Currently, the capability detection of L3 cache Non-Contiguous CBM is
missing with OS interface (--iface os). Regardless of whether the
hardware supports it or not, the capability of L3 cache Non-Contiguous
CBM always shows "unsupported":

$ pqos --iface os -d | grep "Non-Contiguous CBM"
                Non-Contiguous CBM: unsupported

Add L3 cache Non-Contiguous CBM capability detection by reading
'sparse_masks' file of L3 cache from kernel resctrl filesystem.

After fix, if the hardware (e.g., Intel, AMD, Hygon platform) supports:
$ pqos --iface os -d | grep "Non-Contiguous CBM"
                Non-Contiguous CBM: supported

Fixes: 0a1dc08 ("Non-Contiguous CBM support")
Signed-off-by: Xiaochen Shen <shenxiaochen@open-hieco.net>
…erface

Currently, the capability detection of L2 cache Non-Contiguous CBM is
missing with OS interface (--iface os). Regardless of whether the
hardware supports it or not, the capability of L2 cache Non-Contiguous
CBM always shows "unsupported":

$ pqos --iface os -d | grep "Non-Contiguous CBM"
                Non-Contiguous CBM: unsupported

Add L2 cache Non-Contiguous CBM capability detection by reading
'sparse_masks' file of L2 cache from kernel resctrl filesystem.

After fix, if the hardware (e.g., some Intel platforms) supports:
$ pqos --iface os -d | grep "Non-Contiguous CBM"
                Non-Contiguous CBM: supported

Fixes: 0a1dc08 ("Non-Contiguous CBM support")
Signed-off-by: Xiaochen Shen <shenxiaochen@open-hieco.net>
@shenxiaochen shenxiaochen force-pushed the fix-non-contiguous-cbm branch from 82762b6 to 678681b Compare January 29, 2026 12:25
@shenxiaochen
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@rkanagar
Git pushed code to fix the coding style issue mentioned in #302 (comment)

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Merged

@rkanagar rkanagar closed this Jan 29, 2026
@shenxiaochen
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Merged

@rkanagar Thank you very much for help!

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4 participants