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3 changes: 0 additions & 3 deletions cpu_forwarded/stage_decode.v
Original file line number Diff line number Diff line change
Expand Up @@ -75,9 +75,6 @@ module stage_decode(input clk,

wire [31:0] reg_file_write_data;

wire [31:0] read_data_0;
wire [31:0] read_data_1;

wire reg_file_write_en;

pipelined_basic_register_file_control
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3 changes: 0 additions & 3 deletions cpu_forwarded/stage_memory.v
Original file line number Diff line number Diff line change
Expand Up @@ -62,9 +62,6 @@ module stage_memory(
.write_enable(main_mem_wen),
.clk(clk));

wire [31:0] write_back_register_input;
wire [31:0] exe_result;

mem_result_control mem_res_control(.instr_type(current_instr_type),
.read_data(read_data_1),
.alu_result(alu_result),
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3 changes: 0 additions & 3 deletions pipelined_basic/stage_decode.v
Original file line number Diff line number Diff line change
Expand Up @@ -73,9 +73,6 @@ module stage_decode(input clk,

wire [31:0] reg_file_write_data;

wire [31:0] read_data_0;
wire [31:0] read_data_1;

wire reg_file_write_en;

pipelined_basic_register_file_control
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3 changes: 0 additions & 3 deletions pipelined_basic/stage_memory.v
Original file line number Diff line number Diff line change
Expand Up @@ -62,9 +62,6 @@ module stage_memory(
.write_enable(main_mem_wen),
.clk(clk));

wire [31:0] write_back_register_input;
wire [31:0] exe_result;

mem_result_control mem_res_control(.instr_type(current_instr_type),
.read_data(read_data_1),
.alu_result(alu_result),
Expand Down