Prepare verilator 4.020

[jlusiardi]

With Verilator 4.020 some errors are found during compilation like:

%Error: pipelined_basic/stage_decode.v:76: Duplicate declaration of signal: 'read_data_0'
                                         : ... note: ANSI ports must have type declared with the I/O (IEEE 2017 23.2.2.2)
   wire [31:0]        read_data_0;
                      ^~~~~~~~~~~
        pipelined_basic/cpu_pipelined_basic.v:98: ... note: In file included from cpu_pipelined_basic.v
        pipelined_basic/stage_decode.v:22: ... Location of original declaration
                    output [31:0] read_data_0,
                                  ^~~~~~~~~~~

Test are good.