Verilog: create symbol_exprt without ID_base_name field
#1465
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The type checker now re-creates the symbol expressions, which removes the ID_base_name field. In turn, this enables more re-use in all the flattening solvers.
tautschnig
approved these changes
Dec 7, 2025
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The type checker now re-creates the symbol expressions, which removes the
ID_base_namefield. In turn, this enables more re-use in all the flattening solvers.