@@ -1338,9 +1338,7 @@ exprt verilog_typecheck_exprt::convert_symbol(
13381338 {
13391339 // A parameter, or enum. The type is elaborated recursively.
13401340 elaborate_symbol_rec (symbol->name );
1341- expr.type () = symbol->type ;
1342- expr.set_identifier (symbol->name );
1343- return std::move (expr);
1341+ return symbol->symbol_expr ().with_source_location (expr);
13441342 }
13451343 else if (symbol->type .id () == ID_verilog_genvar)
13461344 {
@@ -1366,20 +1364,17 @@ exprt verilog_typecheck_exprt::convert_symbol(
13661364 {
13671365 // A named sequence or property. Create an instance expression,
13681366 // and then flatten it.
1369- expr.type () = symbol->type ;
1370- expr.set_identifier (symbol->name );
1367+ auto symbol_expr = symbol->symbol_expr ().with_source_location (expr);
13711368 auto &declaration =
13721369 to_verilog_sequence_property_declaration_base (symbol->value );
13731370 auto instance =
1374- sva_sequence_property_instance_exprt{expr , {}, declaration}
1371+ sva_sequence_property_instance_exprt{symbol_expr , {}, declaration}
13751372 .with_source_location (expr);
13761373 return flatten_named_sequence_property (instance);
13771374 }
13781375 else
13791376 {
1380- expr.type ()=symbol->type ;
1381- expr.set_identifier (symbol->name );
1382- return std::move (expr);
1377+ return symbol->symbol_expr ().with_source_location (expr);
13831378 }
13841379 }
13851380 else
@@ -1392,9 +1387,7 @@ exprt verilog_typecheck_exprt::convert_symbol(
13921387 warning ().source_location = expr.source_location ();
13931388 warning () << " implicit wire " << symbol->display_name () << eom;
13941389 }
1395- expr.type () = symbol->type ;
1396- expr.set_identifier (symbol->name );
1397- return std::move (expr);
1390+ return symbol->symbol_expr ().with_source_location (expr);
13981391 }
13991392 else
14001393 {
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