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syntax-checks.yaml
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Verilog system tasks and functions are always base names Syntactic checks #3477: Pull request #1457 opened by kroening
1m 39s verilog-identifier-system-task
verilog-identifier-system-task
1m 39s
ebmc language interface implementation for Verilog Syntactic checks #3476: Pull request #1454 synchronize by kroening
1m 25s verilog-language-api
verilog-language-api
1m 25s
Verilog: introduce verilog_function_callt::is_system_function_call() Syntactic checks #3475: Pull request #1456 opened by kroening
1m 32s verilog_function_callt_is_system_function_call
verilog_function_callt_is_system_function_call
1m 32s
Verilog: introduce verilog_identifier_exprt Syntactic checks #3474: Pull request #1455 synchronize by kroening
1m 36s verilog-identifier
verilog-identifier
1m 36s
ebmc language interface implementation for Verilog Syntactic checks #3473: Pull request #1454 synchronize by kroening
1m 39s verilog-language-api
verilog-language-api
1m 39s
ebmc language interface implementation for SMV Syntactic checks #3472: Pull request #1418 synchronize by kroening
1m 27s ebmc_language_api
ebmc_language_api
1m 27s
ebmc language interface implementation for Verilog Syntactic checks #3471: Pull request #1454 opened by kroening
1m 38s verilog-language-api
verilog-language-api
1m 38s
ebmc language interface implementation for SMV Syntactic checks #3470: Pull request #1418 synchronize by kroening
1m 28s ebmc_language_api
ebmc_language_api
1m 28s
Verilog: fix integral vs. bit vector terminology Syntactic checks #3469: Pull request #1449 synchronize by kroening
1m 32s verilog-integral-to-bit-vector
verilog-integral-to-bit-vector
1m 32s
Verilog: fix integral vs. bit vector terminology Syntactic checks #3468: Pull request #1449 synchronize by kroening
1m 34s verilog-integral-to-bit-vector
verilog-integral-to-bit-vector
1m 34s
Verilog: parameter assignments use base name Syntactic checks #3467: Pull request #1453 opened by kroening
1m 33s verilog-param-base-name
verilog-param-base-name
1m 33s
SystemVerilog: use base_name instead of identifier Syntactic checks #3466: Pull request #1452 opened by kroening
5m 35s verilog-assertions-base-name
verilog-assertions-base-name
5m 35s
SystemVerilog: test for time data type Syntactic checks #3465: Pull request #1451 opened by kroening
15m 11s time1
time1
15m 11s
KNOWNBUG test for SystemVerilog typedefs Syntactic checks #3464: Pull request #1450 opened by kroening
10m 19s parameters11
parameters11
10m 19s
Verilog: fix integral vs. bit vector terminology Syntactic checks #3463: Pull request #1449 synchronize by kroening
4m 35s verilog-integral-to-bit-vector
verilog-integral-to-bit-vector
4m 35s
Verilog: fix integral vs. bit vector terminology Syntactic checks #3462: Pull request #1449 opened by kroening
1m 26s verilog-integral-to-bit-vector
verilog-integral-to-bit-vector
1m 26s
AIG generation: ignore Verilog named blocks Syntactic checks #3461: Pull request #1448 opened by kroening
1m 25s netlist-named-block
netlist-named-block
1m 25s
SystemVerilog: type parameter ports Syntactic checks #3460: Pull request #1412 synchronize by kroening
1m 31s type_parameter_ports1
type_parameter_ports1
1m 31s
Verilog: use value field for type parameter declarators Syntactic checks #3459: Pull request #1447 opened by kroening
1m 29s verilog-type-parameters-value
verilog-type-parameters-value
1m 29s
SystemVerilog: KNOWNBUG test for subroutine calls Syntactic checks #3458: Pull request #1446 synchronize by kroening
1m 32s named_parameter_assignment1
named_parameter_assignment1
1m 32s
SystemVerilog: KNOWNBUG test for subroutine calls Syntactic checks #3457: Pull request #1446 synchronize by kroening
1m 28s named_parameter_assignment1
named_parameter_assignment1
1m 28s
SystemVerilog: KNOWNBUG test for subroutine calls Syntactic checks #3456: Pull request #1446 opened by kroening
1m 33s named_parameter_assignment1
named_parameter_assignment1
1m 33s
SystemVerilog: sequence and property ports Syntactic checks #3455: Pull request #1436 synchronize by kroening
1m 28s property-ports
property-ports
1m 28s
SystemVerilog: sequence and property ports Syntactic checks #3454: Pull request #1436 synchronize by kroening
1m 38s property-ports
property-ports
1m 38s
SystemVerilog: checking sequence and property declarations Syntactic checks #3453: Pull request #1445 opened by kroening
1m 22s tc-sequence-property-instances
tc-sequence-property-instances
1m 22s