SystemVerilog: use base_name instead of identifier
#1452
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…cover Assert/assume/cover statements and module items can have an optional label. The label is now stored as base_name, and not identifier, since it is not qualified.
tautschnig
approved these changes
Dec 2, 2025
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Assert/assume/cover statements and module items can have an optional label. The label is now stored as
base_name, and notidentifier, since it is not qualified.