Fix AD7134/AD4134 support

Documentation/devicetree/bindings/iio/adc/adi,ad4134.yaml

@@ -1,3 +1,3 @@
 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
 %YAML 1.2
 ---
@@ -18,8 +18,12 @@
 
 properties:
   compatible:
-    enum:
-      - adi,ad4134
+    oneOf:
+      - const: adi,ad4134
+      - items:
+          - enum:
+              - adi,ad7134
+          - const: adi,ad4134
 
   reg:
     maxItems: 1
@@ -30,6 +34,12 @@
   reset-gpios:
     maxItems: 1
 
+  cs-gpios:
+    description:
+      Used to synchronize devices when two or more ADCs are used for
+      synchronized data sampling.
+    maxItems: 1
+
   clocks:
     maxItems: 1
 
@@ -56,6 +66,15 @@
   iovdd-supply: true
   refin-supply: true
 
+  adi,adc-frame:
+    $ref: /schemas/types.yaml#/definitions/string
+    enum: [ 16-bit, 16-bit+CRC, 24-bit, 24-bit+CRC ]
+    default: 24-bit
+    description:
+      Describes how the ADC data packet should be configured. The data packet
+      size is 16-bit when "16-bit" is selected, 24-bit when "16-bit+CRC" or
+      "24-bit" are selected, and 32-bit when "24-bit+CRC" is set.
+
   adi,spi-engine:
     $ref: /schemas/types.yaml#/definitions/phandle
     description: phandle of the SPI slave connected to the SPI engine master
@@ -104,6 +123,7 @@
         iovdd-supply = <&iovdd>;
         refin-supply = <&refin>;
 
+        adi,adc-frame = "24-bit";
         adi,spi-engine = <&ad4134_spi_engine>;
       };
     };

arch/arm/boot/dts/xilinx/zynq-zed-adv7511-ad3552r-hs.dts

@@ -50,7 +50,7 @@
 };
 
 &fpga_axi {
-	ref_clk: clock-controller@44B00000 {
+	ref_clk: spi-clock-controller@44B00000 {
 		compatible = "adi,axi-clkgen-2.00.a";
 		reg = <0x44B00000 0x10000>;
 		#clock-cells = <0>;

arch/arm/boot/dts/xilinx/zynq-zed-adv7511-ad4000.dtsi

@@ -94,7 +94,7 @@
 		clocks = <&clkc 17>;
 	};
 
-	spi_clk: clock-controller@0x44a70000 {
+	spi_clk: spi-clock-controller@0x44a70000 {
 		compatible = "adi,axi-clkgen-2.00.a";
 		reg = <0x44a70000 0x10000>;
 		#clock-cells = <0>;

arch/arm/boot/dts/xilinx/zynq-zed-adv7511-ad4030-24.dts

@@ -58,7 +58,7 @@
 		clocks = <&clkc 15>;
 	};
 
-	spi_clk: clock-controller@44a70000 {
+	spi_clk: spi-clock-controller@44a70000 {
 		compatible = "adi,axi-clkgen-2.00.a";
 		reg = <0x44a70000 0x10000>;
 		#clock-cells = <0>;

arch/arm/boot/dts/xilinx/zynq-zed-adv7511-ad4032-24.dts

@@ -58,7 +58,7 @@
 		clocks = <&clkc 15>;
 	};
 
-	spi_clk: clock-controller@44a70000 {
+	spi_clk: spi-clock-controller@44a70000 {
 		compatible = "adi,axi-clkgen-2.00.a";
 		reg = <0x44a70000 0x10000>;
 		#clock-cells = <0>;

arch/arm/boot/dts/xilinx/zynq-zed-adv7511-ad4134-16.dts

@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Analog Devices AD7134
+ * https://wiki.analog.com/resources/tools-software/linux-drivers/iio-adc/ad4134
+ * https://wiki.analog.com/resources/eval/user-guides/ad4134
+ *
+ * hdl_project: <ad7134_fmc/zed>
+ *
+ * Copyright (C) 2024 Analog Devices, Inc.
+ */
+/dts-v1/;
+
+#include "zynq-zed-adv7511-ad4134-24.dts"
+
+&spi0 {
+	status = "okay";
+
+    ad4134: adc@0 {
+        adi,adc-frame = "16-bit";
+    };
+};

arch/arm/boot/dts/xilinx/zynq-zed-adv7511-ad4134-16CRC.dts

@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Analog Devices AD7134
+ * https://wiki.analog.com/resources/tools-software/linux-drivers/iio-adc/ad4134
+ * https://wiki.analog.com/resources/eval/user-guides/ad4134
+ *
+ * hdl_project: <ad7134_fmc/zed>
+ *
+ * Copyright (C) 2024 Analog Devices, Inc.
+ */
+/dts-v1/;
+
+#include "zynq-zed-adv7511-ad4134-24.dts"
+
+&spi0 {
+	status = "okay";
+
+    ad4134: adc@0 {
+        adi,adc-frame = "16-bit+CRC";
+    };
+};

arch/arm/boot/dts/xilinx/zynq-zed-adv7511-ad4134-24.dts

@@ -0,0 +1,144 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Analog Devices AD4134
+ * https://wiki.analog.com/resources/tools-software/linux-drivers/iio-adc/ad4134
+ * https://wiki.analog.com/resources/eval/user-guides/ad4134
+ *
+ * hdl_project: <ad4134_fmc/zed>
+ *
+ * Copyright (C) 2022 Analog Devices, Inc.
+ */
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+
+#include "zynq-zed.dtsi"
+#include "zynq-zed-adv7511.dtsi"
+
+/ {
+	avdd5: regulator-avdd5 {
+		compatible = "regulator-fixed";
+		regulator-name = "avdd5";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		regulator-always-on;
+	};
+
+	avdd1v8: regulator-avdd1v8 {
+		compatible = "regulator-fixed";
+		regulator-name = "avdd1v8";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		regulator-always-on;
+	};
+
+	iovdd: regulator-iovdd {
+		compatible = "regulator-fixed";
+		regulator-name = "iovdd";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		regulator-always-on;
+	};
+
+	refin: regulator-refin {
+		compatible = "regulator-fixed";
+		regulator-name = "refin";
+		regulator-min-microvolt = <4096000>;
+		regulator-max-microvolt = <4096000>;
+		regulator-always-on;
+	};
+
+	trigger_pwm: adc-pwm-trigger {
+		compatible = "pwm-trigger";
+		#trigger-source-cells = <0>;
+		pwms = <&ad4134_odr_generator 0 1000000 0>;
+	};
+
+	clocks {
+		cnv_ext_clk: ext-clk {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <48000000>;
+			clock-output-names = "cnv_ext_clk";
+		};
+	};
+};
+
+&fpga_axi {
+	rx_dma: dma-controller@44a30000 {
+		compatible = "adi,axi-dmac-1.00.a";
+		reg = <0x44a30000 0x1000>;
+		#dma-cells = <1>;
+		interrupt-parent = <&intc>;
+		interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&clkc 15>;
+	};
+
+	axi_spi_engine_0: spi@44a00000 {
+		compatible = "adi,axi-spi-engine-1.00.a";
+		reg = <0x44a00000 0x10000>;
+		interrupt-parent = <&intc>;
+		interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&clkc 15 &spi_clk>;
+		clock-names = "s_axi_aclk", "spi_clk";
+		dmas = <&rx_dma 0>;
+		dma-names = "offload0-rx";
+		trigger-sources = <&trigger_pwm>;
+		#address-cells = <0x1>;
+		#size-cells = <0x0>;
+
+		ad4134_spi_engine: spi_engine@0 {
+			compatible = "adi,ad4134-spi-engine";
+			reg = <0>;
+
+			spi-max-frequency = <50000000>;
+
+			spi-cpha;
+			spi-rx-bus-width = <1>, <1>, <1>, <1>; /* 4 lanes of 1 bit each */
+		};
+	};
+
+	ad4134_odr_generator: pwm@44b00000 {
+		compatible = "adi,axi-pwmgen-2.00.a";
+		reg = <0x44b00000 0x10000>;
+		#pwm-cells = <3>;
+		clocks = <&clkc 15>;
+		clock-names = "axi";
+	};
+
+	spi_clk: spi-clock-controller@44b10000 {
+		compatible = "adi,axi-clkgen-2.00.a";
+		reg = <0x44b10000 0x10000>;
+		#clock-cells = <0>;
+		clocks = <&clkc 15>, <&clkc 15>;
+		clock-names = "clkin1", "s_axi_aclk";
+		clock-output-names = "clkin1", "spi_clk";
+	};
+};
+
+&spi0 {
+	status = "okay";
+
+	ad4134: adc@0 {
+		compatible = "adi,ad4134";
+		reg = <0>;
+
+		spi-max-frequency = <10000000>;
+
+		reset-gpios = <&gpio0 86 GPIO_ACTIVE_LOW>;
+
+		clocks = <&cnv_ext_clk>;
+		clock-names = "cnv_ext_clk";
+
+		pwm-names = "odr";
+		pwms = <&ad4134_odr_generator 1 1000000 0>;
+
+		avdd5-supply = <&avdd5>;
+		avdd1v8-supply = <&avdd1v8>;
+		iovdd-supply = <&iovdd>;
+		refin-supply = <&refin>;
+
+		adi,spi-engine = <&ad4134_spi_engine>;
+		adi,adc-frame = "24-bit";
+	};
+};

arch/arm/boot/dts/xilinx/zynq-zed-adv7511-ad4134-24CRC.dts

@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Analog Devices AD7134
+ * https://wiki.analog.com/resources/tools-software/linux-drivers/iio-adc/ad4134
+ * https://wiki.analog.com/resources/eval/user-guides/ad4134
+ *
+ * hdl_project: <ad7134_fmc/zed>
+ *
+ * Copyright (C) 2024 Analog Devices, Inc.
+ */
+/dts-v1/;
+
+#include "zynq-zed-adv7511-ad4134-24.dts"
+
+&spi0 {
+	status = "okay";
+
+    ad4134: adc@0 {
+        adi,adc-frame = "24-bit+CRC";
+    };
+};