Fix AD7134/AD4134 support#3314
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The clock controller node name conflicts with the DMA clock controller instance in the zynq-zed-adv7511.dtsi file and causes a device probe error. To solve that, prepend application specific info to clock controller node names. Fixes: f3fdbc8 ("arch: dts: rename adi,axi-clkgen-2.00.a nodes to clock-controller") Co-developed-by: Jonathan Santos <Jonathan.Santos@analog.com> Signed-off-by: Jonathan Santos <Jonathan.Santos@analog.com> Signed-off-by: Marcelo Schmitt <marcelo.schmitt@analog.com>
Add device tree property to configure ADC data packet size so drivers can properly configure data channels. Signed-off-by: Marcelo Schmitt <marcelo.schmitt@analog.com>
In projects that contain two ADCs, the synchronization procedure requires a synchronization signal sent to both ADCs. The cs-gpio is used to provide that synchronization signal. Signed-off-by: Marcelo Schmitt <marcelo.schmitt@analog.com>
Signed-off-by: Marcelo Schmitt <marcelo.schmitt@analog.com>
Include header file for error macros used in the AD4134 driver. Fixes: 5d5bac7 ("iio: adc: ad4134: add AD4134 driver") Signed-off-by: Ioan-daniel Pop <Pop.Ioan-daniel@analog.com> Signed-off-by: Marcelo Schmitt <marcelo.schmitt@analog.com>
The AD4134 and AD7134 support four different data packet frame configurations: * 16-bit ADC data, * 16-bit ADC data followed by 6 CRC bits, * 24-bit ADC data, * 24-bit ADC data followed by 6 CRC bits. Each configuration leads to a slightly different need of real data bits, storage bits, or data shift. Construct and provide proper IIO channels according to the data frame device tree property. Signed-off-by: Ioan-daniel Pop <Pop.Ioan-daniel@analog.com> Co-developed-by: Marcelo Schmitt <marcelo.schmitt@analog.com Signed-off-by: Marcelo Schmitt <marcelo.schmitt@analog.com>
Add channel extended info for the ODR (Output Data Rate) signal. Signed-off-by: Ioan-daniel Pop <Pop.Ioan-daniel@analog.com> Co-developed-by: Marcelo Schmitt <marcelo.schmitt@analog.com> Signed-off-by: Marcelo Schmitt <marcelo.schmitt@analog.com>
In projects that contain two ADCs, the synchronization procedure requires a synchronization signal sent to both ADCs. The cs-gpio is used to provide that synchronization signal. Signed-off-by: Ioan-daniel Pop <Pop.Ioan-daniel@analog.com> Co-developed-by: Marcelo Schmitt <marcelo.schmitt@analog.com> Signed-off-by: Marcelo Schmitt <marcelo.schmitt@analog.com>
Signed-off-by: Ioan-daniel Pop <Pop.Ioan-daniel@analog.com> Signed-off-by: Marcelo Schmitt <marcelo.schmitt@analog.com>
Signed-off-by: Ioan-daniel Pop <Pop.Ioan-daniel@analog.com> Signed-off-by: Marcelo Schmitt <marcelo.schmitt@analog.com>
Count the number os AD4134/AD7134 compatibles under the SPI controller node to determine how many ADCs are present in hardware. Signed-off-by: Marcelo Schmitt <marcelo.schmitt@analog.com>
Use scoped child device node iterator to simplify code. Signed-off-by: Marcelo Schmitt <marcelo.schmitt@analog.com>
Signed-off-by: Ioan-daniel Pop <Pop.Ioan-daniel@analog.com> Co-developed-by: Marcelo Schmitt <marcelo.schmitt@analog.com> Signed-off-by: Marcelo Schmitt <marcelo.schmitt@analog.com>
__iio_device_register() fails if the device has no initialized info field. Assign ad4134_info to all devices (even those that don't expose the channels). Signed-off-by: Marcelo Schmitt <marcelo.schmitt@analog.com>
…optional ODR PWM is used for triggering SPI-Engine offload which then allows adjustable ADC sample rate. However, there exist AD7134 evaluation boards that featute two AD7134 devices that can synchronize to do simultaneous sampling. In those setups, the SPI-Engine offload trigger can be shared between devices and thus the PWM becomes optional for one of them. Also, it is expected that there will be evaluation boards featuring two AD4134 in the future. Extract PWM setup to own routine and make PWMs optional. Co-developed-by: Dragos Bogdan <dragos.bogdan@analog.com> Signed-off-by: Dragos Bogdan <dragos.bogdan@analog.com> Signed-off-by: Ioan-daniel Pop <Pop.Ioan-daniel@analog.com> Co-developed-by: Marcelo Schmitt <marcelo.schmitt@analog.com> Signed-off-by: Marcelo Schmitt <marcelo.schmitt@analog.com>
Make AD4134/AD7134 devices able to provide GPIOs as a GPIO controller. AD4134/AD7134 GPIO controller capability is used by the CN0561 project. Signed-off-by: Ioan-daniel Pop <Pop.Ioan-daniel@analog.com> Signed-off-by: Marcelo Schmitt <marcelo.schmitt@analog.com>
Signed-off-by: Marcelo Schmitt <marcelo.schmitt@analog.com>
Change the duty cycle of the AXI PWM generator used as ODR signal to be equal to dev_ad4134 branch that is said to work for single AD4134 device setup. Signed-off-by: Marcelo Schmitt <marcelo.schmitt@analog.com>
Remove call to sys_clk_rate(). With that ad4134_setup() becomes essentially equal to ad4134_setup() in dev_ad4134 branch which is said to work for AD4134 single device setup. Signed-off-by: Marcelo Schmitt <marcelo.schmitt@analog.com>
Previous implementation that was said to work has all IIO channels configured to use 32-bit storage for each buffer element. That was the last significant remaining difference from dev_ad4134 branch. Preliminary tests suggests the results are now similar to that working version. Signed-off-by: Marcelo Schmitt <marcelo.schmitt@analog.com>
…bits Set SPI transfer bits_per_word equal to number of ADC precision bits (realbits) plus number of CRC bits. _storebits == _realbits + CRC bits .shift = ((_storebits) - (_realbits)) Thus, .realbits + .shift == total number of data bits to transfer. Note .storagebits = 32 to cope with DMA datum element size. Signed-off-by: Marcelo Schmitt <marcelo.schmitt@analog.com>
…_sync" Update dual device setup synchronization attribute name to "ad4134_sync" according to request from Ahmet Alincak and the Apps team. Signed-off-by: Marcelo Schmitt <marcelo.schmitt@analog.com>
Set static visibility to AD4134 GPIO setup routine so to fix build warning. Signed-off-by: Marcelo Schmitt <marcelo.schmitt@analog.com>
Old AD4134 offload support doesn't work anymore with new in-kernel interfaces. Rewrite AD4134 offload support with upstream quality code. iio: adc: ad4134: [WIP] Drop no longer used _ad4134_set_odr() _ad4134_set_odr() was replaced by ad4134_update_conversion_rate(). iio: adc: ad4134: Mix/merge new offload support with old setup procedures iio: adc: ad4134: [WIP] Drop old no longer used PWM devices iio: adc: ad4134: [WIP] Adapt to weird dt configuration iio: adc: ad4134: Check adi,spi-engine instead of dma for offload connection With the update to upstream offload support and trigger sources, the ADC dt node no longer keeps references to DMA. What actually indicates the connection to SPI Engine is the adi,spi-engine property. Check the spi-engine prop to decide whether to configure offload or not. iio: adc: ad4134: Drop old offload support iio: adc: ad4134: Add ad4134_offload_attribute_group iio: adc: ad4134: Set st->num_dout_lines = 4 Signed-off-by: Marcelo Schmitt <marcelo.schmitt@analog.com>
Only setup SPI offloading after having a handle to the device connected to SPI Engine. Signed-off-by: Marcelo Schmitt <marcelo.schmitt@analog.com>
…ffload Use the pointer to the device connected to SPI Engine to configure SPI offloading. Signed-off-by: Marcelo Schmitt <marcelo.schmitt@analog.com>
Use the handle to the device connected to SPI Engine to optimize (i.e. configure for offloading) SPI messages. Signed-off-by: Marcelo Schmitt <marcelo.schmitt@analog.com>
"odr_set_freq" is not standard IIO ABI and is no longer used for sampling frequency configuration. Thus, the leftover extended attribute might only cause confusion. Drop it. Signed-off-by: Marcelo Schmitt <marcelo.schmitt@analog.com>
Output the correct sampling frequency value with the new SPI offload support. Signed-off-by: Marcelo Schmitt <marcelo.schmitt@analog.com>
Previously, AD4134 driver would cause a kernel oops if no offload capable device was obtained at device probe. Properly error out if SPI offload is not available. Signed-off-by: Marcelo Schmitt <marcelo.schmitt@analog.com>
Add device tree for AD7134 (with 16-bit precision) on ZedBoard. Signed-off-by: Ioan-daniel Pop <Pop.Ioan-daniel@analog.com> Co-developed-by: Marcelo Schmitt <marcelo.schmitt@analog.com> Signed-off-by: Marcelo Schmitt <marcelo.schmitt@analog.com>
Add device tree for AD7134 (with 16-bit precision and CRC check) on ZedBoard. Signed-off-by: Ioan-daniel Pop <Pop.Ioan-daniel@analog.com> Co-developed-by: Marcelo Schmitt <marcelo.schmitt@analog.com> Signed-off-by: Marcelo Schmitt <marcelo.schmitt@analog.com>
Add device tree for the CN0561 project on ZedBoard. The featured ADC is AD7134. Signed-off-by: Ioan-daniel Pop <Pop.Ioan-daniel@analog.com> Co-developed-by: Marcelo Schmitt <marcelo.schmitt@analog.com> Signed-off-by: Marcelo Schmitt <marcelo.schmitt@analog.com>
… AD4134 setup Signed-off-by: Marcelo Schmitt <marcelo.schmitt@analog.com>
With the driver updates to support dual AD7134 setup, the clock phandle and name have been changed. Update AD4134 dts clock phandle and name to match the names used in AD7134 dts and provide the names the driver expects. Signed-off-by: Marcelo Schmitt <marcelo.schmitt@analog.com>
The updates to ad4134 driver have added a requirement on a PWM which is used for AD7134 projects (single and duo device setups). The ad4134_fmc HDL project seems to provide/set the PWM trigger too so add that to the dts for AD4134. Signed-off-by: Marcelo Schmitt <marcelo.schmitt@analog.com>
Set cnv_ext_clk (which is used as system clock) to 100 MHz as documented in AD4134-FMC HDL project page [1]. 48 MHz clock lead to insuficient trigger_pwm phase value which, among other things, caused ODR and DCLK signal to not be synchronized resulting in incorrect data read from the ADC. [1]: https://analogdevicesinc.github.io/hdl/projects/ad4134_fmc/index.html Signed-off-by: Marcelo Schmitt <marcelo.schmitt@analog.com>
With faster system clock, increase SPI data clock rate (both SPI Engine and ADC) to achieve faster sample rates. Signed-off-by: Marcelo Schmitt <marcelo.schmitt@analog.com>
Add clock output name to AXI clock generator node so the whole dts becomes equal to zynq-zed-adv7511-ad4134-24.dts in dev_ad4134 branch which was said to work for AD4134 single device setup. Signed-off-by: Marcelo Schmitt <marcelo.schmitt@analog.com>
Add precision bits to AD4134 dts name to better distinguish it from different AD4134 dts that are going to be added in follow up patches. Signed-off-by: Marcelo Schmitt <marcelo.schmitt@analog.com>
Signed-off-by: Marcelo Schmitt <marcelo.schmitt@analog.com>
arm: dts [SQUASH] offload Signed-off-by: Marcelo Schmitt <marcelo.schmitt@analog.com>
Fix clock phandles used by ODR PWM device node. Signed-off-by: Marcelo Schmitt <marcelo.schmitt@analog.com>
Don't use the deprecated legacy SPI Engine anymore. Use the new/updated one instead. Signed-off-by: Marcelo Schmitt <marcelo.schmitt@analog.com>
Bump PWM Generator to version 2. Fix clock phandles used by ODR PWM device node. Signed-off-by: Marcelo Schmitt <marcelo.schmitt@analog.com>
arm: dts [SQUASH] ad7134 offload Signed-off-by: Marcelo Schmitt <marcelo.schmitt@analog.com>
Adjust AXI clock generator names and output names making it follow the same configuration as in zynq-zed-adv7511-ad4134-24.dts. Signed-off-by: Marcelo Schmitt <marcelo.schmitt@analog.com>
Adjust AXI clock generator names and output names making it follow the same configuration as in zynq-zed-adv7511-ad4134-24.dts. Signed-off-by: Marcelo Schmitt <marcelo.schmitt@analog.com>
Bump PWM Generator to version 2. Fix clock phandles used by ODR PWM device node. Signed-off-by: Marcelo Schmitt <marcelo.schmitt@analog.com>
arm: dts: [SQUASH] cn0561 offload Signed-off-by: Marcelo Schmitt <marcelo.schmitt@analog.com>
Add device tree for high speed sample rate data capture support with AD4134. Signed-off-by: Marcelo Schmitt <marcelo.schmitt@analog.com>
Signed-off-by: Marcelo Schmitt <marcelo.schmitt@analog.com>
Fix the declared frequency of the external clock provided to AD7134. Signed-off-by: Marcelo Schmitt <marcelo.schmitt@analog.com>
Fix the declared frequency of the external clock provided to AD7134. Signed-off-by: Marcelo Schmitt <marcelo.schmitt@analog.com>
Set read bus width to 4 lines. Signed-off-by: Marcelo Schmitt <marcelo.schmitt@analog.com>
Set read bus width to 8 lines. Signed-off-by: Marcelo Schmitt <marcelo.schmitt@analog.com>
Previously, the PWM Generator was deriving the output signals from the external 48 MHz clock. That in turn was leading to insuficient ODR high time due to fewer FPGA clock ticks delay being configured for PWM duty cycle. Set AXI FPGA clock as reference for the PWM Generator. Now, having 100 MHz AXI FPGA clock as base clock for the PWM Generator, the ODR waveform duty takes 13 clock ticks delay which results in 130 ns ODR high time. Thus, meeting ODR timing requirements. Signed-off-by: Marcelo Schmitt <marcelo.schmitt@analog.com>
The PWM dt-bindings now accept an optional 3rd specifier (which is typically the PWM polarity flag). Although this 3rd specifier is not supported by the AXI PWM generator, the PWM users in this device tree do provide all the 3 cell specifiers. Signed-off-by: Marcelo Schmitt <marcelo.schmitt@analog.com>
Previously, the PWM Generator was deriving the output signals from the external 48 MHz clock. That in turn was leading to insuficient ODR high time due to fewer FPGA clock ticks delay being configured for PWM duty cycle. Set AXI FPGA clock as reference for the PWM Generator. Now, having 100 MHz AXI FPGA clock as base clock for the PWM Generator, the ODR waveform duty takes 13 clock ticks delay which results in 130 ns ODR high time. Thus, meeting ODR timing requirements. Signed-off-by: Marcelo Schmitt <marcelo.schmitt@analog.com>
The PWM dt-bindings now accept an optional 3rd specifier (which is typically the PWM polarity flag). Although this 3rd specifier is not supported by the AXI PWM generator, the PWM users in this device tree do provide all the 3 cell specifiers. Signed-off-by: Marcelo Schmitt <marcelo.schmitt@analog.com>
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PR Description
Updates on upstream Linux SPI Engine and PWM interfaces broke the previous/current support for AD7134/AD4134. Update AD7134/AD4134 device driver and device tree files to work on kernel 6.12.
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