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hmc7044: add dynamic PLL2 rate selection via CCF #3283

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hmc7044: add dynamic PLL2 rate selection via CCF #3283

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5a0b518
iio: frequency: hmc7044: register pll2 clock
vai-tomme Apr 8, 2026
98d9c12
iio: frequency: hmc7044: split pll2 configuration to separate function
vai-tomme Apr 8, 2026
540d57d
dt-bindings: iio: frequency: hmc7044: add adi,set-rate-parent
vai-tomme May 4, 2026
9a5b8f2
iio: frequency: hmc7044: support set rate parent
vai-tomme May 4, 2026
389d0ad
iio: frequency: hmc7044: drop determine rate implementation
vai-tomme Apr 8, 2026
e040364
iio: frequency: hmc7044: split clk register to separate function
vai-tomme Apr 21, 2026
d7d2a4d
iio: frequency: hmc7044: support round rate with parent rate
vai-tomme Apr 8, 2026
b9ef879
iio: frequency: hmc7044: use clk framework for rate changes
vai-tomme Apr 8, 2026
68fc04d
iio: frequency: hmc7044: support zero output frequency
vai-tomme Apr 8, 2026
e42adad
Documentation: bindings: hmc7044: add adi,max-deviation-ppm
vai-tomme Apr 6, 2024
30964aa
iio: frequency: hmc7044: support channel frequency deviation setting
vai-tomme Apr 8, 2026
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7 changes: 7 additions & 0 deletions Documentation/devicetree/bindings/iio/frequency/hmc7044.txt
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Original file line number Diff line number Diff line change
Expand Up @@ -142,6 +142,13 @@ Adding channels:
0 - Internal resistor disable.
1 - Internal 100 Ω resistor enable per output pin.
3 - Internal 50 Ω resistor enable per output pin.
- adi,set-rate-parent: Propagate clock rate change to parent. If set,
this will, if needed, change rate of parent (PLL2) to fulfill
the frequency rate request.
- adi,max-deviation-ppm: Maximum allowed deviation in parts-per-million
when changing channel output frequencies. A rate change request
that would cause deviation larger than allowed value for any
output channel with this property, is blocked.

Example:

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