hmc7044: add dynamic PLL2 rate selection via CCF#3283

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vai-tomme wants to merge 11 commits into

analogdevicesinc:mainfrom

vai-tomme:upstream/hmc7044

Commits on Apr 27, 2026

iio: frequency: hmc7044: register pll2 clock
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committed

Commits on May 4, 2026

iio: frequency: hmc7044: split pll2 configuration to separate function
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dt-bindings: iio: frequency: hmc7044: add adi,set-rate-parent
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iio: frequency: hmc7044: support set rate parent
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iio: frequency: hmc7044: drop determine rate implementation
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iio: frequency: hmc7044: split clk register to separate function
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iio: frequency: hmc7044: support round rate with parent rate
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iio: frequency: hmc7044: use clk framework for rate changes
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iio: frequency: hmc7044: support zero output frequency
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Documentation: bindings: hmc7044: add adi,max-deviation-ppm
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iio: frequency: hmc7044: support channel frequency deviation setting
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