AD9088 API v2.0.0 Update & Related Changes

Documentation/devicetree/bindings/iio/adc/adi,ad9088.yaml

@@ -0,0 +1,249 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/adi,ad9088.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Analog Devices AD9088 Mixed Signal Front End (MxFE)
+
+maintainers:
+  - Michael Hennerich <michael.hennerich@analog.com>
+
+description: |
+  Bindings for the Analog Devices AD9088 and compatible MxFE devices.
+
+properties:
+  compatible:
+    enum:
+      - adi,ad9084
+      - adi,ad9088
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    maxItems: 1
+
+  clock-names:
+    const: dev_clk
+    description: Device clock name
+
+  '#clock-cells':
+    const: 0
+
+  clock-output-names:
+    maxItems: 1
+
+  adi,spi-3wire-enable:
+    type: boolean
+    description: Enable 3-wire SPI mode.
+
+  adi,device-profile-fw-name:
+    $ref: /schemas/types.yaml#/definitions/string
+    description: Name of the device profile firmware file.
+
+  adi,rx-real-channel-en:
+    type: boolean
+    description: Enable real RX channel mode (complex if not present).
+
+  adi,tx-real-channel-en:
+    type: boolean
+    description: Enable real TX channel mode (complex if not present).
+
+  adi,side-b-use-seperate-tpl-en:
+    type: boolean
+    description: Use separate TPL for side B.
+
+  adi,hsci-auto-linkup-mode-en:
+    type: boolean
+    description: Enable HSCI auto linkup mode.
+
+  adi,hsci-disable-after-boot-en:
+    type: boolean
+    description: Disable HSCI after initial configuration.
+
+  adi,multidevice-instance-count:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description: Number of multidevice instances.
+
+  adi,trigger-sync-en:
+    type: boolean
+    description: Enable trigger synchronization.
+
+  adi,standalone-enable:
+    type: boolean
+    description: Enable standalone mode.
+
+  adi,nyquist-zone:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    enum: [1, 2]
+    description: Nyquist zone (1 or 2).
+
+  adi,jtx0-logical-lane-mapping:
+    minItems: 12
+    maxItems: 12
+    items:
+      $ref: /schemas/types.yaml#/definitions/uint32
+    description: Logical lane mapping for JTX0.
+
+  adi,jtx1-logical-lane-mapping:
+    minItems: 12
+    maxItems: 12
+    items:
+      $ref: /schemas/types.yaml#/definitions/uint32
+    description: Logical lane mapping for JTX1.
+
+  adi,jrx0-physical-lane-mapping:
+    minItems: 12
+    maxItems: 12
+    items:
+      $ref: /schemas/types.yaml#/definitions/uint32
+    description: Physical lane mapping for JRX0.
+
+  adi,jrx1-physical-lane-mapping:
+    minItems: 12
+    maxItems: 12
+    items:
+      $ref: /schemas/types.yaml#/definitions/uint32
+    description: Physical lane mapping for JRX1.
+
+  adi,jtx-ser-amplitude:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description: Serializer amplitude setting.
+
+  adi,jtx-ser-pre-emphasis:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description: Serializer pre-emphasis setting.
+
+  adi,jtx-ser-post-emphasis:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description: Serializer post-emphasis setting.
+
+  adi,subclass:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description: JESD subclass setting.
+
+  adi,gpio-hop-profile:
+    minItems: 1
+    maxItems: 5
+    items:
+      $ref: /schemas/types.yaml#/definitions/uint32
+    description: |
+      GPIO indices for frequency hopping profile selection.
+      Supports up to 5 GPIOs for profile control. Missing values
+      are filled with -1 (ADI_APOLLO_GPIO_HOP_IDX_NONE).
+
+  adi,gpio-hop-block:
+    minItems: 1
+    maxItems: 4
+    items:
+      $ref: /schemas/types.yaml#/definitions/uint32
+    description: |
+      GPIO indices for frequency hopping block selection.
+      Supports up to 4 GPIOs for block control. Missing values
+      are filled with -1 (ADI_APOLLO_GPIO_HOP_IDX_NONE).
+
+  adi,gpio-hop-side:
+    maxItems: 1
+    items:
+      $ref: /schemas/types.yaml#/definitions/uint32
+    description: |
+      GPIO index for frequency hopping side selection.
+      Supports 1 GPIO for side control. Missing value is
+      filled with -1 (ADI_APOLLO_GPIO_HOP_IDX_NONE).
+
+  adi,gpio-hop-slice:
+    minItems: 1
+    maxItems: 5
+    items:
+      $ref: /schemas/types.yaml#/definitions/uint32
+    description: |
+      GPIO indices for frequency hopping slice selection.
+      Supports up to 5 GPIOs for slice control. Missing values
+      are filled with -1 (ADI_APOLLO_GPIO_HOP_IDX_NONE).
+
+  adi,gpio-hop-terminal:
+    minItems: 1
+    maxItems: 4
+    items:
+      $ref: /schemas/types.yaml#/definitions/uint32
+    description: |
+      GPIO indices for frequency hopping terminal selection.
+      Supports up to 4 GPIOs for terminal control. Missing values
+      are filled with -1 (ADI_APOLLO_GPIO_HOP_IDX_NONE).
+
+  adi,gpio-sniffer-a-export:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description: |
+      GPIO pin number for FFT sniffer side A done signal export.
+      Used to export FFT done status to external GPIO pin.
+      Defaults to 17 if not specified.
+
+  adi,gpio-sniffer-b-export:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description: |
+      GPIO pin number for FFT sniffer side B done signal export.
+      Used to export FFT done status to external GPIO pin.
+      Defaults to 18 if not specified.
+
+required:
+  - compatible
+  - adi,device-profile-fw-name
+
+additionalProperties: false
+
+allOf:
+  - $ref: /schemas/spi/spi-peripheral-props.yaml#
+  - $ref: /schemas/jesd204/jesd204-device-props.yaml#
+
+examples:
+  - |
+    #include <dt-bindings/iio/adc/adi,ad9088.h>
+
+    spi {
+      #address-cells = <1>;
+      #size-cells = <0>;
+
+      trx0_ad9084: ad9084@0 {
+        #address-cells = <1>;
+        #size-cells = <0>;
+        compatible = "adi,ad9084";
+        reg = <0>;
+        spi-max-frequency = <5000000>;
+
+        /* Clocks */
+        clocks = <&adf4382 0>;
+        clock-names = "dev_clk";
+        dev_clk-clock-scales = <1 10>;
+
+        clock-output-names = "rx_sampl_clk", "tx_sampl_clk";
+        #clock-cells = <1>;
+
+        adi,axi-hsci-connected = <&axi_hsci>;
+
+        adi,hsci-auto-linkup-mode-en;
+        adi,hsci-disable-after-boot-en;
+
+        jesd204-device;
+        #jesd204-cells = <2>;
+        jesd204-top-device = <0>; /* This is the TOP device */
+        jesd204-ignore-errors;
+
+        jesd204-link-ids = <DEFRAMER_LINK_A0_TX FRAMER_LINK_A0_RX>;
+
+        jesd204-inputs =
+          <&axi_ad9084_core_rx 0 FRAMER_LINK_A0_RX>,
+          <&axi_ad9084_core_tx 0 DEFRAMER_LINK_A0_TX>;
+
+        reset-gpios = <&axi_gpio 62 0>;
+        adi,device-profile-fw-name = "DEVICE_PROFILE_NAME";
+
+        /* GPIO frequency hopping configuration (optional) */
+        adi,gpio-hop-profile = <19 20 21 22 23>;
+        adi,gpio-hop-block = <15 16 17 18>;
+
+        /* FFT sniffer GPIO exports (optional) */
+        adi,gpio-sniffer-a-export = <17>;
+        adi,gpio-sniffer-b-export = <18>;
+      };
+    };

Documentation/devicetree/bindings/iio/frequency/adi,adf4382.yaml

@@ -0,0 +1,141 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/frequency/adi,adf4382.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ADF4382 Microwave Wideband Synthesizer with Integrated VCO
+
+maintainers:
+  - Antoniu Miclaus <antoniu.miclaus@analog.com>
+  - Ciprian Hegbeli <ciprian.hegbeli@analog.com>
+
+description: The ADF4382 is a high performance, ultralow jitter, Frac-N PLL with
+   integrated VCO ideally suited for LO generation for 5G applications
+   or data converter clock applications.
+
+   https://www.analog.com/en/products/adf4382a.html
+
+properties:
+  compatible:
+    enum:
+      - adi,adf4382
+      - adi,adf4382a
+
+  reg:
+    maxItems: 1
+
+  spi-max-frequency:
+    maximum: 75000000
+
+  clocks:
+    description: Clock to provide CLKIN reference clock signal.
+    maxItems: 1
+
+  clock-names:
+    description:
+      External clock that provides reference input frequency.
+    items:
+      - const: ref_clk
+
+  '#clock-cells':
+    const: 0
+
+  clock-output-names:
+    maxItems: 1
+
+  adi,charge-pump-microamp:
+    description:
+      The charge pump current that the external loop filter was designed for.
+      If this property is not specified, then the charge pump current is set to the
+      default 11100uA. The valid values are listed below. However, if the set value is
+      not supported, the driver will look for the closest valid charge pump current.
+    anyOf:
+      - enum: [790, 990, 1190, 1380, 1590, 1980, 2390, 2790, 3180, 3970, 4770, 5570, 6330, 7910, 9510, 11100]
+
+  adi,ref-divider:
+    description:
+      Input divider of the reference frequency, cannot be lower then 1 or
+      higher then 63.
+    allOf:
+      - $ref: /schemas/types.yaml#/definitions/uint32
+      - minimum: 1
+      - maximum: 63
+      - default: 1
+    maxItems: 1
+
+  adi,ref-doubler-enable:
+    description:
+      Enables the doubling of the reference clock.
+    type: boolean
+    maxItems: 1
+
+  adi,bleed-word:
+    description:
+      A small programmable constant charge pump current, known as bleed current,
+      can be used to optimize the phase noise and fractional spurious signals
+      in fractional mode.
+    allOf:
+      - $ref: /schemas/types.yaml#/definitions/uint32
+      - minimum: 0
+      - maximum: 4095
+      - default: 0
+    maxItems: 1
+
+  adi,power-up-frequency:
+    description:
+      PLL tunes to the set frequency on probe or defaults to 2,305 GHz.
+    allOf:
+      - $ref: /schemas/types.yaml#/definitions/uint64
+      - minimum: 687500000
+      - maximum: 22000000000
+      - default: 2305000000
+    maxItems: 1
+
+  adi,output-power-value:
+    description:
+      The output power amplitude level which will be applied for both channels
+      at startup.
+    allOf:
+      - $ref: /schemas/types.yaml#/definitions/uint32
+      - minimum: 0
+      - maximum: 15
+      - default: 11
+    maxItems: 1
+
+  adi,spi-3wire-enable:
+    description:
+      Uses SPI in 3 wire mode, by default is uses 4 wire mode.
+    type: boolean
+    maxItems: 1
+
+  adi,cmos-3v3:
+    description:
+      Sets the SPI logic to 3.3V, by defautl it uses 1,8V.
+    type: boolean
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - clock-names
+
+additionalProperties: false
+
+examples:
+  - |
+    spi {
+        #address-cells = <1>;
+        #size-cells = <0>;
+        frequency@0 {
+          compatible = "adi,adf4382";
+          reg = <0>;
+          spi-max-frequency = <1000000>;
+          clocks = <&adf4382_clkin>;
+          clock-names = "ref_clk";
+          adi,charge-pump-current = <15>;
+          adi,ref-divider = <1>;
+        };
+    };
+...