AD9088 API v2.0.0 Update & Related Changes#3179
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mhennerich wants to merge 60 commits intostaging/xlnx/ad9084-dev-rebasefrom
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AD9088 API v2.0.0 Update & Related Changes#3179mhennerich wants to merge 60 commits intostaging/xlnx/ad9084-dev-rebasefrom
mhennerich wants to merge 60 commits intostaging/xlnx/ad9084-dev-rebasefrom
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Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
Document common properties of the JESD FSM framework. Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
This adds support for reading 204C lane latency. Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
This patch adds support for external synchronization in the AXI ADC driver. It introduces detection of external sync capability via the ADI_EXT_SYNC bit in the configuration register. A new sysfs interface is added to control synchronization: - sync_start_enable: allows triggering sync actions (arm, disarm, trigger_manual) depending on hardware capabilities. - sync_start_enable_available: lists available sync actions. These additions enable more flexible synchronization control for multi-device setups and JESD204-based systems. Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
The ADI support for the driver will include a HDL IP which will support 8-bit transfers as well as a different data load address from the base address. To differentiate from the original driver a ID system has been added and changes have been made based on the ID. Signed-off-by: Ciprian Hegbeli <ciprian.hegbeli@analog.com>
The HDL IP can be configured to run in 8, 16 and 32 bit mode. This will extend the capabilities of the current driver to support 16 bit implementations using compatibility strings. Signed-off-by: Ciprian Hegbeli <ciprian.hegbeli@analog.com>
The HDL IP can be configured to run in 8, 16 and 32 bit mode. This will extend the capabilities of the current driver to support 32 bit implementations using compatibility strings. Signed-off-by: Ciprian Hegbeli <ciprian.hegbeli@analog.com>
In case of LTC6952 we need a REFin can VCOin. Assuming VCOin is provided by CCF, add support for setting the desired rate. Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
CPMID should be cleared after init. Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
…ings Add round_rate callback, which seem to be needed. Set required mode bits for integer and fractional mode automatically. Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
When a DMA transfer is done, the vchan_cookie_complete triggers the axi_dmac_desc_free which is called in IRQ context. This triggers the BUG_ON in vunmap function. To solve this issue a workqueue is created to schedule axi_dmac_desc_free to be performed outside of interrupt context. Signed-off-by: Eliza Balas <eliza.balas@analog.com>
The maximum BSYNC output frequency is 200 MHz per the datasheet, not 250 MHz. The previous value of 250 MHz corresponds to the REFIN maximum, not the BSYNC output maximum. Fixes: 54bbd40 ("iio: frequency: support the adf4030 Synchronizer") Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
The datasheet requires resetting the TDC_ERR monitor (set then clear RST_TDC_ERR in Register 0x61 bit 7) before starting a TDC measurement. Without this step, stale error flags from a previous measurement could persist. Fixes: 54bbd40 ("iio: frequency: support the adf4030 Synchronizer") Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
The ADF4030 reports die temperature in sign-magnitude format: Register 0x92 holds the 8-bit magnitude in degrees C and Register 0x93 bit 0 holds the sign (0=positive, 1=negative). The driver was incorrectly using sign_extend32() which assumes two's complement encoding, producing wrong results for negative temperatures. Fixes: 54bbd40 ("iio: frequency: support the adf4030 Synchronizer") Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
…list The datasheet states that AVGEXP values 0, 1, and 2 are not supported, corresponding to averaging counts of 64, 128, and 256. Remove these from the available oversampling ratio list so userspace cannot select them. The minimum supported value is 512 (AVGEXP=3). Fixes: 54bbd40 ("iio: frequency: support the adf4030 Synchronizer") Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
Add a lower bound check for iter_number in adf4030_auto_align_iteration_set(). When iter_number is 0, the expression 'iter_number - 1' underflows since iter_number is u8, resulting in ALIGN_CYCLES being silently set to 7 (8 iterations) instead of returning an error. The register field ALIGN_CYCLES encodes 'desired cycles minus 1', so at least 1 iteration must be requested. Fixes: 54bbd40 ("iio: frequency: support the adf4030 Synchronizer") Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
The output divider (ODIV) valid range is 10 to 4095 per the datasheet. The driver checked only the upper bound. Add the lower bound check against ADI_ADF4030_O_DIV_MIN (10) to reject configurations that would produce an out-of-range divider value. Fixes: 54bbd40 ("iio: frequency: support the adf4030 Synchronizer") Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
The retry counter starts at 3 and decrements on each attempt. The debug message used 'retry - 3' which produces 0 on the first attempt and wraps to large unsigned values on subsequent attempts. Use '4 - retry' to correctly display attempt numbers 1, 2, 3. Fixes: 54bbd40 ("iio: frequency: support the adf4030 Synchronizer") Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
This adds support for BSYNC background serial alignment Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
…iver This adds a new driver for the HSCI found on AD9084 and AD9088 devices. Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
- New driver for LTC6948/LTC6947 Fractional-N Synthesizer with Integrated VCO Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
The ADF4382A is a high performance, ultralow jitter, Frac-N PLL with integrated VCO ideally suited for LO generation for 5G applications or data converter clock applications. The high performance PLL has a figure of merit of -239 dBc/Hz, low 1/f Noise and high PFD frequency of 625MHz in integer mode that can achieve ultralow in-band noise and integrated jitter. The ADF4382A can generate frequencies in a fundamental octave range of 11.5 GHz to 21 GHz, thereby eliminating the need for sub-harmonic filters. The divide by 2 and 4 output dividers on the part allow frequencies to be generated from 5.75GHz to 10.5GHz and 2.875GHz to 5.25GHz respectively. Signed-off-by: Ciprian Hegbeli <ciprian.hegbeli@analog.com>
The ADF4382 is a high performance, ultra-low jitter, fractional-N phased-locked loop (PLL) with an integrated voltage controlled oscillator (VCO) ideally suited for local oscillator (LO) generation for 5G applications or data converter clock applications. Signed-off-by: Ciprian Hegbeli <ciprian.hegbeli@analog.com> Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
Add support for the new AION HDL IP Core. Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
Imply the axi-aion-trig driver. Signed-off-by: Nuno Sá <nuno.sa@analog.com>
Document AD9088 MxFE. Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
Adds all firmware files used by Apollo based propjects. Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
Add a devicetree for the AD9084 VPK180 based project. Signed-off-by: Bogdan Luncan <bogdan.luncan@analog.com>
Add support to Fast Frequency Hopping Signed-off-by: Jorge Marques <jorge.marques@analog.com>
Add IIO driver for the AD9084 Buffer Memory (BMEM) interface which provides high-speed data capture from the device's internal SRAM buffers. The AD9084 contains multiple BMEM instances (A0, A1, B0, B1) each with 128KB of SRAM that can capture samples from the HSDIN/ADC data path. This driver exposes these as IIO channels with triggered buffer support. Key features: - 4 IIO voltage channels mapped to BMEM instances A0/A1/B0/B1 - Configurable 16-bit or 32-bit sample sizes - Programmable capture address ranges (0-32K words) - Per-channel delay sample configuration - Delay hop support with 4 profiles for timing control - Continuous capture mode using delayed workqueues - Per-channel buffer allocation and demultiplexing - RX MUX configuration for proper ADC routing The driver implements the IIO buffer interface, allowing userspace applications to enable channels and read captured samples through the standard IIO buffer mechanism. Capture is triggered via the Apollo trigger subsystem and samples are read via SPI/HSCI access to the BMEM SRAM. Configuration is exposed through: - IIO sysfs: sampling_frequency, delay configuration per channel - Debugfs: bmem_sel, start/end addresses, sample_size, delay_start The driver uses the Apollo API (adi_apollo_bmem_*) for hardware configuration and follows the standard IIO buffer setup pattern with postenable/predisable callbacks. Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
This patch introduces support for configuring BMEM sample delays for
both CDDC and FDDC paths on the AD9088 device. It adds new IIO
extended attributes:
- main_bmem_sample_delay (CDDC)
- channel_bmem_sample_delay (FDDC)
These attributes allow reading and writing sample delay values via
sysfs. The implementation includes:
* Validation of device tree properties (adi,cddc-bmem-sample-delay-en
and adi,fddc-bmem-sample-delay-en).
* Range clamping (0–4095 for CDDC, 0–255 for FDDC).
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
Implement a complete calibration data management system that allows saving and restoring all device calibration data across power cycles. Features: - Structured binary file format with header, sections, and CRC32 - Saves ADC, DAC, SERDES RX, and SERDES TX calibration data - Supports both 4T4R and 8T8R device configurations - Validates chip ID, device config, and data integrity on restore - Accessible via sysfs bin attribute for easy integration File format (v1): +--------------------+ | Header (64 bytes) | <- Magic, version, chip ID, offsets, sizes +--------------------+ | ADC Cal Data | <- Sequential + random modes for all ADCs +--------------------+ | DAC Cal Data | <- All DAC channels +--------------------+ | SERDES RX Cal Data | <- All SERDES RX 12-packs +--------------------+ | SERDES TX Cal Data | <- All SERDES TX 12-packs +--------------------+ | CRC32 (4 bytes) | <- Integrity checksum +--------------------+ Sysfs interface: /sys/bus/spi/devices/spi*.*/iio:device*/calibration_data Usage: # Save calibration data cat .../calibration_data > /lib/firmware/ad9088_cal.bin # Restore calibration data cat /lib/firmware/ad9088_cal.bin > .../calibration_data Implementation details: 1. ad9088_cal.c: - ad9088_cal_save(): Reads all calibration data from hardware - ad9088_cal_restore(): Writes calibration data back to hardware - Uses API functions from adi_apollo_cfg.c for data access - Comprehensive validation and error checking 2. ad9088.c: - ad9088_cal_data_read(): Sysfs read handler - ad9088_cal_data_write(): Sysfs restore handler - Caches calibration data for multiple reads - Mutex protection for thread safety 3. File format features: - Magic number (0x41443930 = "AD90") for validation - Version field for future compatibility - Per-section offsets and sizes for flexible parsing - Device-specific metadata (chip ID, 4T4R/8T8R config) - CRC32 checksum for data integrity Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
Add a new debugfs related interface: - PRBS generator and checker configuration - 2D eye scan functionality - Device info queries (API version, UUID, die ID, chip info, temp) - HSCI enable control - JTX lane drive swing and emphasis controls - JRX phase adjustment calculation - MCS tracking status/validation Functions exported for use by debugfs: - ad9088_print_sysref_phase() New function in ad9088_debugfs.c: - ad9088_debugfs_register() - ad9088_status_show() - ad9088_mcs_track_cal_status_print() - ad9088_mcs_tracking_cal_validate() Signed-off-by: Michael Hennerich <michael.hennerich@analog.com> Signed-off-by: Nuno Sá <nuno.sa@analog.com>
Added the defconfig for the ADSY1100 VPX card. Signed-off-by: Ciprian Hegbeli <ciprian.hegbeli@analog.com>
Add configuration for AD9084 Versal based projects. Signed-off-by: Ciprian Hegbeli <ciprian.hegbeli@analog.com>
Add default config for microblaze apollo builds. While at it, add a small update on the base microblaze defconfig. Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
A command-line utility for inspecting and validating AD9088 calibration data files. Signed-off-by: Michael Hennerich <michael.hennerich@analog.com> Signed-off-by: Nuno Sá <nuno.sa@analog.com>
…0.1.3 Added: - API - Added support for AD9088 - API - Support for a new Profile format that consolidates and improves the data structures used by the part - this is a breaking change for Profile versions prior to V10. See Components Section below for Profile version - API - Integrated support for external trigger-based frequency hopping - API - New function to read part number with X-grade or B-grade and SW trim information (SW Trim 1/3/5) - FW - Allow ADC/DAC PN signal inversion based on user Profile settings Changed: - API - Some code cleanup and optimization by deleting unused code - API - Converted frequency representations from Hz to uHz (microhertz) throughout the ADF4030 driver and example code - this is a breaking change - FW - Upgrade device Profile. See Components Section below for Profile version - FW - For SerDes Rx, a number of bridging cal settings come from device Profile - FW - Device clock frequency variable changed from kHz to Hz - FW - Define the P-N inversion of the differential ADC/DAC RFIO in the device Profile - FW - 4D slice mode switching optimization - FW - Optimized receiver handling of overrange signal conditions Deprecated: - API - adi_apollo_clk_mcs_internal_sysref_per_set(), sync_logic_reset(), adi_apollo_jrx_subclass_set(), adi_apollo_clk_mcs_trig_reset_serdes_enable(), adi_apollo_adc_tlines_offset_set(), hsci_regio_rmw_write32() Fixed: - API - Bug fixed in adi_apollo_tmode_config_set(). Previously, the function ignored the resolution parameter and always set 16-bit resolution - API - Bug fixed in adi_apollo_cnco_profile_load() whereby an incorrect value could be written to the Profile when less than a full Profile array was being loaded - API - Bug fixed in tx_txpath_misc_configure() whereby register values were not updated - API - Increased delay after freezing of ADC background calibration before executing ADC slice mode switch within the slice mode switch prepare API function - FW - Bug fixed whereby MCS side-B was not being updated correctly during tracking calibration with dual clocking Errata: - API - ADF4030-FPGA Time-of-Flight measurement may time out when operating at low BSYNC frequencies - API - AD9084-SE ADC performance has not been fully optimized Supported: - AD9088 - AD9084 Components: - Device Driver API 2.0.10 - Firmware 2.0.6 - Device Profile 10.1.28 Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
…SREF divider Add adi,subclass = <1> to all four TRX nodes and compute LTC6953_AION_BSYNC_6_DIVIDER dynamically from FREQ_J1_MHz / SYSREF_CLK_MHz. Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
…amping Update ADF4382_PHASE_BLEED_CNST_DIV from 285 to 250 and replace the simple 8-bit mask with proper bounds checking and clamping for the phase adjust register value. Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
… to u32 Add debugfs read/write support for mcs_track_decimation allowing runtime adjustment of the MCS tracking calibration TDC decimation rate. Change mcs_track_decimation from u16 to u32 to match the API. Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
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PR Description
API & Firmware Update
Debugfs & DT
DTS
Other