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3 changes: 3 additions & 0 deletions .gitmodules
Original file line number Diff line number Diff line change
Expand Up @@ -13,3 +13,6 @@
[submodule "designs/src/liteeth/dev/liteeth"]
path = designs/src/liteeth/dev/repo
url = https://github.com/enjoy-digital/liteeth.git
[submodule "designs/src/cnn/dev/repo"]
path = designs/src/cnn/dev/repo
url = https://github.com/NNgen/nngen
38 changes: 38 additions & 0 deletions designs/asap7/cnn/config.mk
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All DESIGN_HOME vars need to be replaced with BENCH_DESIGN_HOME

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export DESIGN_NICKNAME ?= cnn
export DESIGN_NAME = cnn
export PLATFORM = asap7

-include $(BENCH_DESIGN_HOME)/src/$(DESIGN_NAME)/verilog.mk

#export SYNTH_HIERARCHICAL ?= 1

export SYNTH_HIERARCHICAL = 1
export RTLMP_RPT_DIR = reports/$(PLATFORM)/cnn/base/rtlmp/
#export SYNTH_MINIMUM_KEEP_SIZE ?= 10000

export SDC_FILE = $(BENCH_DESIGN_HOME)/$(PLATFORM)/cnn/constraint.sdc

ifeq ($(BLOCKS),)
export ADDITIONAL_LEFS = $(sort $(wildcard $(BENCH_DESIGN_HOME)/src/$(DESIGN_NAME)/fakeram_*.lef))
export ADDITIONAL_LIBS = $(sort $(wildcard $(BENCH_DESIGN_HOME)/src/$(DESIGN_NAME)/fakeram_*.lib))
endif

#export CORE_UTILIZATION = 40
export DIE_AREA = 0 0 600 600
export CORE_AREA = 10 10 590 590
#
#export PLACE_DENSITY_LB_ADDON = 0.10

#export IO_CONSTRAINTS = $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/io.tcl
export PLACE_PINS_ARGS = -min_distance 30 -min_distance_in_tracks
export MACRO_PLACE_HALO = 6 6
export MACRO_BLOCKAGE_HALO = 0.5
#export MACRO_ROWS_HALO_X = 0.5
#export MACRO_ROWS_HALO_Y = 0.5

#export MACRO_PLACEMENT = $(BENCH_DESIGN_HOME)/$(PLATFORM)/cnn/macro.cfg

#export TNS_END_PERCENT = 100
#
#export CTS_CLUSTER_SIZE = 10
#export CTS_CLUSTER_DIAMETER = 50
19 changes: 19 additions & 0 deletions designs/asap7/cnn/constraint.sdc
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current_design cnn

set clk_name clk
set clk_port_name CLK
set clk_period 1000
set clk_io_pct 0.125

set clk_port [get_ports $clk_port_name]

create_clock -name $clk_name -period $clk_period $clk_port

set non_clock_inputs [all_inputs -no_clocks]
set_input_delay 10 -clock $clk_name $non_clock_inputs
set_output_delay 10 -clock $clk_name [all_outputs]

set_driving_cell -lib_cell DFFHQNx2_ASAP7_75t_R -pin QN $non_clock_inputs
set dff_d_cap 0.683716
set_load [expr 4.0 * $dff_d_cap] [all_outputs]

70 changes: 70 additions & 0 deletions designs/asap7/cnn/rules-base.json
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{
"synth__design__instance__area__stdcell": {
"value": 2947.89,
"compare": "<="
},
"constraints__clocks__count": {
"value": 1,
"compare": "=="
},
"placeopt__design__instance__area": {
"value": 3109,
"compare": "<="
},
"placeopt__design__instance__count__stdcell": {
"value": 11777,
"compare": "<="
},
"detailedplace__design__violations": {
"value": 0,
"compare": "=="
},
"cts__design__instance__count__setup_buffer": {
"value": 1024,
"compare": "<="
},
"cts__design__instance__count__hold_buffer": {
"value": 1024,
"compare": "<="
},
"globalroute__antenna_diodes_count": {
"value": 0,
"compare": "<="
},
"detailedroute__route__wirelength": {
"value": 83651,
"compare": "<="
},
"detailedroute__route__drc_errors": {
"value": 0,
"compare": "<="
},
"detailedroute__antenna__violating__nets": {
"value": 0,
"compare": "<="
},
"detailedroute__antenna_diodes_count": {
"value": 5,
"compare": "<="
},
"finish__timing__setup__ws": {
"value": -44.21,
"compare": ">="
},
"finish__design__instance__area": {
"value": 3180,
"compare": "<="
},
"finish__timing__drv__setup_violation_count": {
"value": 512,
"compare": "<="
},
"finish__timing__drv__hold_violation_count": {
"value": 100,
"compare": "<="
},
"finish__timing__wns_percent_delay": {
"value": -10.0,
"compare": ">="
}
}
202 changes: 202 additions & 0 deletions designs/src/cnn/LICENSE
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@@ -0,0 +1,202 @@

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