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Fix vf counts #3

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1 change: 1 addition & 0 deletions LICENSE
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Original file line number Diff line number Diff line change
@@ -1,3 +1,4 @@
Copyright (c) 2026, Jeffery Lim
Copyright (c) 2024, Scott Smith
Copyright (c) 2019-2023, The Regents of the University of California.
All rights reserved.
Expand Down
7 changes: 6 additions & 1 deletion fpga/common/rtl/cpl_queue_manager.v
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Expand Up @@ -31,6 +31,8 @@ module cpl_queue_manager #
parameter QUEUE_PTR_WIDTH = 16,
// Function ID index width (log2 of number of function IDs)
parameter FUNCTION_ID_WIDTH = 8, // Scott
// Number of Functions (252 VF, 4 PF)
parameter F_COUNT = 252+1,
// Filter the Event Queue Pointer
parameter FILTER_EQ_PTR = 1, // Scott
// Log queue size field width
Expand Down Expand Up @@ -127,7 +129,10 @@ parameter CL_OP_TABLE_SIZE = $clog2(OP_TABLE_SIZE);

parameter CL_CPL_SIZE = $clog2(CPL_SIZE);

parameter EVENT_QUEUES_PER_FUNC = (2**EVENT_WIDTH) / (2**FUNCTION_ID_WIDTH); // Scott
// Round F_COUNT up to nearest power of 2
parameter NUM_FUNCS = 2**($clog2(F_COUNT));

parameter EVENT_QUEUES_PER_FUNC = (2**EVENT_WIDTH) / (NUM_FUNCS); // Scott
parameter LOG_QUEUES_PER_FUNC = FILTER_EQ_PTR == 1 ? $clog2(EVENT_QUEUES_PER_FUNC) : 2; // Scott

// Scott: Change total size to be 136 to hold VF ID
Expand Down
17 changes: 14 additions & 3 deletions fpga/common/rtl/mqnic_core.v
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Expand Up @@ -32,7 +32,8 @@ module mqnic_core #

// SRIOV Configuration
parameter FUNCTION_ID_WIDTH = 8, // Scott
parameter NUM_FUNCS = FUNCTION_ID_WIDTH == 8 ? 252 : 2**FUNCTION_ID_WIDTH,
// Number of Functions (252 VF, 4 PF)
parameter F_COUNT = 252+1,

parameter PORT_COUNT = IF_COUNT*PORTS_PER_IF,

Expand Down Expand Up @@ -699,10 +700,15 @@ wire [AXIL_CTRL_DATA_WIDTH-1:0] ctrl_reg_rd_data_int;
wire ctrl_reg_rd_wait_int;
wire ctrl_reg_rd_ack_int;

// user bus
wire [FUNCTION_ID_WIDTH-1:0] ctrl_reg_wr_user;
wire [FUNCTION_ID_WIDTH-1:0] ctrl_reg_rd_user;

axil_reg_if #(
.DATA_WIDTH(AXIL_CTRL_DATA_WIDTH),
.ADDR_WIDTH(AXIL_CSR_ADDR_WIDTH),
.STRB_WIDTH(AXIL_CTRL_STRB_WIDTH),
.USER_WIDTH(FUNCTION_ID_WIDTH),
.TIMEOUT(4)
)
axil_reg_if_inst (
Expand All @@ -713,6 +719,7 @@ axil_reg_if_inst (
* AXI-Lite slave interface
*/
.s_axil_awaddr(axil_csr_awaddr),
.s_axil_awuser(axil_csr_awuser),
.s_axil_awprot(axil_csr_awprot),
.s_axil_awvalid(axil_csr_awvalid),
.s_axil_awready(axil_csr_awready),
Expand All @@ -724,6 +731,7 @@ axil_reg_if_inst (
.s_axil_bvalid(axil_csr_bvalid),
.s_axil_bready(axil_csr_bready),
.s_axil_araddr(axil_csr_araddr),
.s_axil_aruser(axil_csr_aruser),
.s_axil_arprot(axil_csr_arprot),
.s_axil_arvalid(axil_csr_arvalid),
.s_axil_arready(axil_csr_arready),
Expand All @@ -738,10 +746,12 @@ axil_reg_if_inst (
.reg_wr_addr(ctrl_reg_wr_addr),
.reg_wr_data(ctrl_reg_wr_data),
.reg_wr_strb(ctrl_reg_wr_strb),
.reg_wr_user(ctrl_reg_wr_user),
.reg_wr_en(ctrl_reg_wr_en),
.reg_wr_wait(ctrl_reg_wr_wait_int),
.reg_wr_ack(ctrl_reg_wr_ack_int),
.reg_rd_addr(ctrl_reg_rd_addr),
.reg_rd_user(ctrl_reg_rd_user),
.reg_rd_en(ctrl_reg_rd_en),
.reg_rd_data(ctrl_reg_rd_data_int),
.reg_rd_wait(ctrl_reg_rd_wait_int),
Expand Down Expand Up @@ -803,7 +813,7 @@ always @(posedge clk) begin
8'h20: ctrl_reg_rd_data_reg <= BUILD_DATE; // FW ID: Build date
8'h24: ctrl_reg_rd_data_reg <= GIT_HASH; // FW ID: Git commit hash
8'h28: ctrl_reg_rd_data_reg <= RELEASE_INFO; // FW ID: Release info
8'h2C: ctrl_reg_rd_data_reg <= NUM_FUNCS; // FW ID: total functions
8'h2C: ctrl_reg_rd_data_reg <= F_COUNT; // FW ID: total functions
// IRQ configuration
8'h40: ctrl_reg_rd_data_reg <= 32'h0000C007; // IRQ config: Type
8'h44: ctrl_reg_rd_data_reg <= 32'h00000100; // IRQ config: Version
Expand Down Expand Up @@ -3248,7 +3258,8 @@ generate
.AXIS_IF_RX_USER_WIDTH(AXIS_IF_RX_USER_WIDTH),

// SRIOV Configuration Scott
.FUNCTION_ID_WIDTH(FUNCTION_ID_WIDTH)
.FUNCTION_ID_WIDTH(FUNCTION_ID_WIDTH),
.F_COUNT(F_COUNT)
)
interface_inst (
.clk(clk),
Expand Down
14 changes: 9 additions & 5 deletions fpga/common/rtl/mqnic_core_pcie.v
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Expand Up @@ -785,6 +785,7 @@ if (APP_ENABLE) begin : pcie_tlp_mux
.fifo_half_full(),
.fifo_watermark()
);


pcie_tlp_mux #(
.PORTS(2),
Expand Down Expand Up @@ -1288,12 +1289,12 @@ wire [AXIL_MSIX_ADDR_WIDTH-1:0] axil_msix_awaddr_translated;
wire [AXIL_MSIX_ADDR_WIDTH-1:0] axil_msix_araddr_translated;
wire [FUNCTION_ID_WIDTH-1:0] axil_msix_read_function_id;
wire [FUNCTION_ID_WIDTH-1:0] axil_msix_write_function_id;

// Scott
resource_translator #(
.TOTAL_RESOURCES(2**(FUNCTION_ID_WIDTH + IRQ_INDEX_WIDTH)),
.TOTAL_RESOURCES(2**($clog2(F_COUNT) + IRQ_INDEX_WIDTH + 1)),
.FUNCTION_ID_WIDTH(FUNCTION_ID_WIDTH),
.RESOURCE_BIT_WIDTH(32'd2), // 4-bits per cpl queue
.F_COUNT(F_COUNT),
.RESOURCE_BIT_WIDTH(32'd3), // 4-bits per cpl queue
.AXIL_ADDR_WIDTH(AXIL_MSIX_ADDR_WIDTH)
)
pcie_msix_resource_translator (
Expand All @@ -1312,12 +1313,14 @@ pcie_msix_resource_translator (
);

pcie_msix #(
.IRQ_INDEX_WIDTH(FUNCTION_ID_WIDTH + IRQ_INDEX_WIDTH), // Scott
.IRQ_INDEX_WIDTH(IRQ_INDEX_WIDTH), // Scott
.AXIL_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH),
.AXIL_ADDR_WIDTH(AXIL_MSIX_ADDR_WIDTH),
.AXIL_STRB_WIDTH(AXIL_CTRL_STRB_WIDTH),
.TLP_HDR_WIDTH(TLP_HDR_WIDTH),
.TLP_FORCE_64_BIT_ADDR(TLP_FORCE_64_BIT_ADDR)
.TLP_FORCE_64_BIT_ADDR(TLP_FORCE_64_BIT_ADDR),
.FUNCTION_ID_WIDTH(FUNCTION_ID_WIDTH),
.F_COUNT(F_COUNT)
)
pcie_msix_inst (
.clk(clk),
Expand Down Expand Up @@ -1643,6 +1646,7 @@ mqnic_core #(

// SRIOV Configuration
.FUNCTION_ID_WIDTH(FUNCTION_ID_WIDTH), // Scott
.F_COUNT(F_COUNT),

.PORT_COUNT(PORT_COUNT),

Expand Down
34 changes: 26 additions & 8 deletions fpga/common/rtl/mqnic_interface.v
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Expand Up @@ -104,6 +104,7 @@ module mqnic_interface #

// SRIOV Configuration Function ID Width
parameter FUNCTION_ID_WIDTH = 8, // Scott
parameter F_COUNT = 252 + 1,

// Interrupt configuration
parameter IRQ_INDEX_WIDTH = EQN_WIDTH - FUNCTION_ID_WIDTH,
Expand Down Expand Up @@ -1031,10 +1032,15 @@ wire [REG_DATA_WIDTH-1:0] ctrl_reg_rd_data;
wire ctrl_reg_rd_wait;
wire ctrl_reg_rd_ack;

wire [FUNCTION_ID_WIDTH-1:0] ctrl_reg_wr_user;
wire [FUNCTION_ID_WIDTH-1:0] ctrl_reg_rd_user;


axil_reg_if #(
.DATA_WIDTH(REG_DATA_WIDTH),
.ADDR_WIDTH(REG_ADDR_WIDTH),
.STRB_WIDTH(REG_STRB_WIDTH),
.USER_WIDTH(FUNCTION_ID_WIDTH),
.TIMEOUT(4)
)
axil_reg_if_inst (
Expand All @@ -1045,7 +1051,7 @@ axil_reg_if_inst (
* AXI-Lite slave interface
*/
.s_axil_awaddr(axil_ctrl_awaddr),
// .s_axil_awuser(axil_ctrl_awuser), // Scott
.s_axil_awuser(axil_ctrl_awuser), // Scott
.s_axil_awprot(axil_ctrl_awprot),
.s_axil_awvalid(axil_ctrl_awvalid),
.s_axil_awready(axil_ctrl_awready),
Expand All @@ -1057,7 +1063,7 @@ axil_reg_if_inst (
.s_axil_bvalid(axil_ctrl_bvalid),
.s_axil_bready(axil_ctrl_bready),
.s_axil_araddr(axil_ctrl_araddr),
// .s_axil_aruser(axil_ctrl_aruser), // Scott
.s_axil_aruser(axil_ctrl_aruser), // Scott
.s_axil_arprot(axil_ctrl_arprot),
.s_axil_arvalid(axil_ctrl_arvalid),
.s_axil_arready(axil_ctrl_arready),
Expand All @@ -1072,10 +1078,12 @@ axil_reg_if_inst (
.reg_wr_addr(ctrl_reg_wr_addr),
.reg_wr_data(ctrl_reg_wr_data),
.reg_wr_strb(ctrl_reg_wr_strb),
.reg_wr_user(ctrl_reg_wr_user),
.reg_wr_en(ctrl_reg_wr_en),
.reg_wr_wait(ctrl_reg_wr_wait),
.reg_wr_ack(ctrl_reg_wr_ack),
.reg_rd_addr(ctrl_reg_rd_addr),
.reg_rd_user(ctrl_reg_rd_user),
.reg_rd_en(ctrl_reg_rd_en),
.reg_rd_data(ctrl_reg_rd_data),
.reg_rd_wait(ctrl_reg_rd_wait),
Expand Down Expand Up @@ -1181,6 +1189,7 @@ always @(posedge clk) begin
end
RBB+8'h10: ctrl_reg_rd_data_reg <= PORTS; // IF ctrl: Port count
RBB+8'h14: ctrl_reg_rd_data_reg <= SCHEDULERS; // IF ctrl: Scheduler count
RBB+8'h18: ctrl_reg_rd_data_reg <= ctrl_reg_rd_user; // IF ctrl: Assigned MAC/VF ID
RBB+8'h20: ctrl_reg_rd_data_reg <= MAX_TX_SIZE; // IF ctrl: Max TX MTU
RBB+8'h24: ctrl_reg_rd_data_reg <= MAX_RX_SIZE; // IF ctrl: Max RX MTU
RBB+8'h28: ctrl_reg_rd_data_reg <= tx_mtu_reg; // IF ctrl: TX MTU
Expand Down Expand Up @@ -1441,6 +1450,7 @@ wire [FUNCTION_ID_WIDTH-1:0] axil_eqm_write_function_id;
resource_translator #(
.TOTAL_RESOURCES(2**EQN_WIDTH),
.FUNCTION_ID_WIDTH(FUNCTION_ID_WIDTH),
.F_COUNT(F_COUNT),
.RESOURCE_BIT_WIDTH(32'd4), // 4-bits per cpl queue
.AXIL_ADDR_WIDTH(AXIL_ADDR_WIDTH)
)
Expand Down Expand Up @@ -1469,6 +1479,7 @@ cpl_queue_manager #(
.EVENT_WIDTH(IRQ_INDEX_WIDTH),
.QUEUE_PTR_WIDTH(QUEUE_PTR_WIDTH),
.FUNCTION_ID_WIDTH(FUNCTION_ID_WIDTH), // Scott
.F_COUNT(F_COUNT),
.FILTER_EQ_PTR(0), // EQ points to IRQ -> does not need to be translated
.LOG_QUEUE_SIZE_WIDTH(LOG_QUEUE_SIZE_WIDTH),
.CPL_SIZE(EVENT_SIZE),
Expand Down Expand Up @@ -1713,6 +1724,7 @@ wire [FUNCTION_ID_WIDTH-1:0] axil_cqm_write_function_id;
resource_translator #(
.TOTAL_RESOURCES(2**CQN_WIDTH),
.FUNCTION_ID_WIDTH(FUNCTION_ID_WIDTH),
.F_COUNT(F_COUNT),
.RESOURCE_BIT_WIDTH(32'd4), // 4-bits per cpl queue
.AXIL_ADDR_WIDTH(AXIL_ADDR_WIDTH)
)
Expand All @@ -1722,7 +1734,7 @@ cpl_queue_resource_translator_inst(
.input_write_function_id(axil_cqm_awuser),

.input_read_address(axil_cqm_araddr),
.input_read_function_id(axil_eqm_aruser),
.input_read_function_id(axil_cqm_aruser),

.output_read_address(axil_cqm_araddr_translated),
.output_write_address(axil_cqm_awaddr_translated),
Expand All @@ -1741,6 +1753,7 @@ cpl_queue_manager #(
.EVENT_WIDTH(EQN_WIDTH),
.QUEUE_PTR_WIDTH(QUEUE_PTR_WIDTH),
.FUNCTION_ID_WIDTH(FUNCTION_ID_WIDTH), // Scott
.F_COUNT(F_COUNT),
.FILTER_EQ_PTR(1), // CQ points to EQ -> needs to be translated
.LOG_QUEUE_SIZE_WIDTH(LOG_QUEUE_SIZE_WIDTH),
.CPL_SIZE(CPL_SIZE),
Expand Down Expand Up @@ -1989,6 +2002,7 @@ wire [FUNCTION_ID_WIDTH-1:0] axil_tx_qm_write_function_id;
resource_translator #(
.TOTAL_RESOURCES(2**TX_QUEUE_INDEX_WIDTH),
.FUNCTION_ID_WIDTH(FUNCTION_ID_WIDTH),
.F_COUNT(F_COUNT),
.RESOURCE_BIT_WIDTH(32'd5), // 5-bits per queue
.AXIL_ADDR_WIDTH(AXIL_ADDR_WIDTH)
)
Expand Down Expand Up @@ -2018,6 +2032,7 @@ queue_manager #(
.CPL_INDEX_WIDTH(CQN_WIDTH),
.QUEUE_PTR_WIDTH(QUEUE_PTR_WIDTH),
.FUNCTION_ID_WIDTH(FUNCTION_ID_WIDTH), // Scott
.F_COUNT(F_COUNT),
.LOG_QUEUE_SIZE_WIDTH(LOG_QUEUE_SIZE_WIDTH),
.DESC_SIZE(DESC_SIZE),
.LOG_BLOCK_SIZE_WIDTH(LOG_BLOCK_SIZE_WIDTH),
Expand Down Expand Up @@ -2071,8 +2086,8 @@ tx_qm_inst (
/*
* AXI-Lite slave interface
*/
.s_axil_awaddr(axil_tx_qm_awaddr),
.s_axil_awuser(axil_tx_qm_awuser), // Scott
.s_axil_awaddr(axil_tx_qm_awaddr_translated),
.s_axil_awuser(axil_tx_qm_write_function_id), // Scott
.s_axil_awprot(axil_tx_qm_awprot),
.s_axil_awvalid(axil_tx_qm_awvalid),
.s_axil_awready(axil_tx_qm_awready),
Expand All @@ -2083,8 +2098,8 @@ tx_qm_inst (
.s_axil_bresp(axil_tx_qm_bresp),
.s_axil_bvalid(axil_tx_qm_bvalid),
.s_axil_bready(axil_tx_qm_bready),
.s_axil_araddr(axil_tx_qm_araddr),
.s_axil_aruser(axil_tx_qm_aruser), // Scott
.s_axil_araddr(axil_tx_qm_araddr_translated),
.s_axil_aruser(axil_tx_qm_read_function_id), // Scott
.s_axil_arprot(axil_tx_qm_arprot),
.s_axil_arvalid(axil_tx_qm_arvalid),
.s_axil_arready(axil_tx_qm_arready),
Expand All @@ -2107,6 +2122,7 @@ wire [FUNCTION_ID_WIDTH-1:0] axil_rx_qm_write_function_id;
resource_translator #(
.TOTAL_RESOURCES(2**RX_QUEUE_INDEX_WIDTH),
.FUNCTION_ID_WIDTH(FUNCTION_ID_WIDTH),
.F_COUNT(F_COUNT),
.RESOURCE_BIT_WIDTH(32'd5), // 5-bits per queue
.AXIL_ADDR_WIDTH(AXIL_ADDR_WIDTH)
)
Expand Down Expand Up @@ -2134,6 +2150,7 @@ queue_manager #(
.CPL_INDEX_WIDTH(CQN_WIDTH),
.QUEUE_PTR_WIDTH(QUEUE_PTR_WIDTH),
.FUNCTION_ID_WIDTH(FUNCTION_ID_WIDTH), // Scott
.F_COUNT(F_COUNT),
.LOG_QUEUE_SIZE_WIDTH(LOG_QUEUE_SIZE_WIDTH),
.DESC_SIZE(DESC_SIZE),
.LOG_BLOCK_SIZE_WIDTH(LOG_BLOCK_SIZE_WIDTH),
Expand Down Expand Up @@ -2941,7 +2958,8 @@ mqnic_interface_rx #(
.AXIS_RX_USER_WIDTH(AXIS_IF_RX_USER_WIDTH),

// SRIOV config
.FUNCTION_ID_WIDTH(FUNCTION_ID_WIDTH) // Scott
.FUNCTION_ID_WIDTH(FUNCTION_ID_WIDTH), // Scott
.F_COUNT(F_COUNT)
)
interface_rx_inst (
.clk(clk),
Expand Down
6 changes: 4 additions & 2 deletions fpga/common/rtl/mqnic_interface_rx.v
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Expand Up @@ -83,7 +83,8 @@ module mqnic_interface_rx #
parameter AXIS_RX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TS_WIDTH : 0) + 1,

// SRIOV config
parameter FUNCTION_ID_WIDTH = 8
parameter FUNCTION_ID_WIDTH = 8,
parameter F_COUNT = 252 + 1
)
(
input wire clk,
Expand Down Expand Up @@ -378,7 +379,8 @@ rx_engine #(
.AXIS_RX_ID_WIDTH(AXIS_RX_ID_WIDTH),
.AXIS_RX_DEST_WIDTH(AXIS_RX_DEST_WIDTH),
.AXIS_RX_USER_WIDTH(INT_AXIS_RX_USER_WIDTH),
.FUNCTION_ID_WIDTH(FUNCTION_ID_WIDTH)
.FUNCTION_ID_WIDTH(FUNCTION_ID_WIDTH),
.F_COUNT(F_COUNT)
)
rx_engine_inst (
.clk(clk),
Expand Down
8 changes: 6 additions & 2 deletions fpga/common/rtl/queue_manager.v
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Expand Up @@ -31,6 +31,8 @@ module queue_manager #
parameter QUEUE_PTR_WIDTH = 16,
// Function ID index width (log2 of number of function IDs)
parameter FUNCTION_ID_WIDTH = 8, // Scott
// Number of Functions (252 VF, 4 PF)
parameter F_COUNT = 252+1,
// Log queue size field width
parameter LOG_QUEUE_SIZE_WIDTH = $clog2(QUEUE_PTR_WIDTH),
// Queue element size
Expand Down Expand Up @@ -122,7 +124,9 @@ module queue_manager #

parameter QUEUE_COUNT = 2**QUEUE_INDEX_WIDTH;

parameter CPL_QUEUES_PER_FUNC = (2**CPL_INDEX_WIDTH) / (2**FUNCTION_ID_WIDTH); // Scott
parameter NUM_FUNCS = 2**($clog2(F_COUNT));

parameter CPL_QUEUES_PER_FUNC = (2**CPL_INDEX_WIDTH) / (NUM_FUNCS); // Scott

parameter LOG_QUEUES_PER_FUNC = $clog2(CPL_QUEUES_PER_FUNC); // Scott

Expand Down Expand Up @@ -519,7 +523,7 @@ always @* begin
queue_ram_be[8] = 1'b1;
end else begin
queue_ram_be[8] = 1'b1;
queue_ram_write_data[71:64] = axil_reg_pipeline_function_id_reg[PIPELINE-1]
queue_ram_write_data[71:64] = axil_reg_pipeline_function_id_reg[PIPELINE-1];
end
end
32'h8002zzzz: begin
Expand Down
5 changes: 3 additions & 2 deletions fpga/common/rtl/resource_translator.v
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Expand Up @@ -14,7 +14,8 @@
// This is the virtual to physical resource translation logic mentioned in the 2024 IEEE Cloud Paper.
module resource_translator # (
parameter TOTAL_RESOURCES = 4096, // The number of resources we are virtualizing
parameter FUNCTION_ID_WIDTH = 8, // Number of functions
parameter FUNCTION_ID_WIDTH = 8, // Function ID Width
parameter F_COUNT = 252+1, // Number of functions
parameter RESOURCE_BIT_WIDTH = 2, // Number of bits per resource (for example, if each resource has a set of relevant addresses)
parameter AXIL_ADDR_WIDTH = 32 // AXIL Address Width

Expand All @@ -36,7 +37,7 @@ module resource_translator # (
wire [AXIL_ADDR_WIDTH-1:0] output_read_address_translated;
wire [AXIL_ADDR_WIDTH-1:0] output_write_address_translated;

parameter TOTAL_FUNCS = 2**FUNCTION_ID_WIDTH;
parameter TOTAL_FUNCS = 2**($clog2(F_COUNT));

parameter RESOURCES_PER_FUNC = TOTAL_RESOURCES / TOTAL_FUNCS;
parameter RESOURCE_PER_FUNC_BITS = $clog2(RESOURCES_PER_FUNC);
Expand Down
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