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a007c03
[AMD] MINIMAX-M3 FP4 vLLM Agentic Support
ajith-sirra-amd Jul 8, 2026
d6be9de
[AMD] MINIMAX-M3 FP4 vLLM Agentic Support. Added PR Link
ajith-sirra-amd Jul 8, 2026
cdac231
[AMD] MINIMAX-M3 FP4 vLLM Agentic Support. Search Space Modification.
ajith-sirra-amd Jul 8, 2026
89daabe
[AMD] MINIMAX-M3 FP4 vLLM Agentic Support. Search Space Modification.
ajith-sirra-amd Jul 8, 2026
c54a190
[AMD] MINIMAX-M3 FP4 vLLM Agentic Support. Search Space Modification.
ajith-sirra-amd Jul 8, 2026
bf6d169
[AMD] MINIMAX-M3 FP4 vLLM Agentic Support. Search Space Modification …
ajith-sirra-amd Jul 8, 2026
8bf107f
[AMD] MINIMAX-M3 FP4 vLLM Agentic Support. Search Space Modification …
ajith-sirra-amd Jul 8, 2026
02cf9fd
[AMD] MINIMAX-M3 FP4 vLLM Agentic Support. Search Space Modification.
ajith-sirra-amd Jul 8, 2026
205732d
chore: remove LMCache backend from MiniMax-M3 FP4 MI355X agentic benc…
seungrokj Jul 9, 2026
ca7be40
Merge branch 'main' into amd/agentx-minimax-m3-vllm
seungrokj Jul 9, 2026
82466e2
chore: revert max-num-seqs to CONC and drop hybrid KV cache flag
seungrokj Jul 9, 2026
4bff323
[AMD] MINIMAX-M3 FP4 vLLM Agentic Support. Search Space Modification.
ajith-sirra-amd Jul 9, 2026
f341572
[AMD] MINIMAX-M3 FP4 vLLM Agentic Support. Removing redundant prefix …
ajith-sirra-amd Jul 9, 2026
4fc1965
Merge branch 'main' into amd/agentx-minimax-m3-vllm
ajith-sirra-amd Jul 9, 2026
9f628cc
[AMD] MINIMAX-M3 FP4 vLLM Agentic Support. Modifying Search Space.
ajith-sirra-amd Jul 9, 2026
7fad233
Merge branch 'amd/agentx-minimax-m3-vllm' of https://github.com/SemiA…
ajith-sirra-amd Jul 9, 2026
7e8ccea
Merge branch 'main' into amd/agentx-minimax-m3-vllm
ajith-sirra-amd Jul 9, 2026
fe31146
Merge branch 'main' into amd/agentx-minimax-m3-vllm
seungrokj Jul 10, 2026
493a0cf
Merge branch 'main' into amd/agentx-minimax-m3-vllm
ajith-sirra-amd Jul 10, 2026
ccb54cd
fix(agentic): preserve matrix CPU DRAM value
cquil11 Jul 10, 2026
cf4bba6
fix(agentic): use explicit MI355X server port
cquil11 Jul 10, 2026
060ec35
fix(agentic): remove recipe env fallbacks
cquil11 Jul 10, 2026
f323281
Merge main into amd/agentx-minimax-m3-vllm
cquil11 Jul 10, 2026
e8ff5ba
fix(configs): restore indentation of dsv4 decode additional-settings
github-actions[bot] Jul 10, 2026
794d8be
Merge branch 'main' into amd/agentx-minimax-m3-vllm
cquil11 Jul 10, 2026
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238 changes: 238 additions & 0 deletions benchmarks/single_node/agentic/minimaxm3_fp4_mi355x.sh
Original file line number Diff line number Diff line change
@@ -0,0 +1,238 @@
#!/usr/bin/env bash
set -euo pipefail
set -x

# Agentic trace replay benchmark for Minimax-M3 FP4 on MI355X using vLLM.
#
# Required env vars:
# MODEL, MODEL_PATH, TP, CONC, KV_OFFLOADING, KV_OFFLOAD_BACKEND,
# TOTAL_CPU_DRAM_GB, RESULT_DIR, DURATION, EP_SIZE, DP_ATTENTION

source "$(dirname "$0")/../../benchmark_lib.sh"

check_env_vars MODEL MODEL_PATH TP CONC KV_OFFLOADING KV_OFFLOAD_BACKEND TOTAL_CPU_DRAM_GB RESULT_DIR DURATION EP_SIZE DP_ATTENTION

echo "MODEL=$MODEL TP=$TP CONC=$CONC KV_OFFLOADING=$KV_OFFLOADING TOTAL_CPU_DRAM_GB=$TOTAL_CPU_DRAM_GB RESULT_DIR=$RESULT_DIR DURATION=$DURATION EP_SIZE=$EP_SIZE DP_ATTENTION=$DP_ATTENTION"

PORT=8888

if [[ -n "${SLURM_JOB_ID+x}" ]]; then
echo "JOB $SLURM_JOB_ID running on $SLURMD_NODENAME"
fi

# ROCR/HIP visibility for vLLM 0.14+
if [[ -n "${ROCR_VISIBLE_DEVICES+x}" ]]; then
export HIP_VISIBLE_DEVICES="$ROCR_VISIBLE_DEVICES"
fi

rocm-smi || true
amd-smi || true

if [[ ! -d "$MODEL_PATH" || -z "$(ls -A "$MODEL_PATH" 2>/dev/null)" ]]; then
hf download "$MODEL" --local-dir "$MODEL_PATH"
fi

resolve_trace_source
install_agentic_deps

# ---- Server config ----------------------------------------------------------
SERVER_LOG="$RESULT_DIR/server.log"
LMCACHE_LOG="$RESULT_DIR/lmcache_server.log"
mkdir -p "$RESULT_DIR"

OFFLOAD_ARGS=(--no-enable-prefix-caching)

# ---- Lmcache config ----------------------------------------------------------
LMCACHE_PID=""

cleanup_lmcache_server() {
if [[ -n "$LMCACHE_PID" ]] && kill -0 "$LMCACHE_PID" 2>/dev/null; then
kill "$LMCACHE_PID" 2>/dev/null || true
wait "$LMCACHE_PID" 2>/dev/null || true
fi
}

trap cleanup_lmcache_server EXIT

wait_for_lmcache_ready() {
{ set +x; } 2>/dev/null
local attempts=120
local tail_pid=""

while [ ! -f "$LMCACHE_LOG" ]; do
if [[ -n "$LMCACHE_PID" ]] && ! kill -0 "$LMCACHE_PID" 2>/dev/null; then
echo "LMCache server died before creating log file. Exiting." >&2
exit 1
fi
sleep 1
done

tail -f -n +1 "$LMCACHE_LOG" &
tail_pid=$!

for ((i = 1; i <= attempts; i++)); do
if curl --output /dev/null --silent --fail "http://127.0.0.1:${LMCACHE_HTTP_PORT}/healthcheck"; then
kill "$tail_pid" 2>/dev/null || true
wait "$tail_pid" 2>/dev/null || true
return 0
fi
if [[ -n "$LMCACHE_PID" ]] && ! kill -0 "$LMCACHE_PID" 2>/dev/null; then
echo "LMCache server died before becoming healthy. Log follows:" >&2
kill "$tail_pid" 2>/dev/null || true
wait "$tail_pid" 2>/dev/null || true
cat "$LMCACHE_LOG" >&2 || true
exit 1
fi
sleep 1
done

echo "Timed out waiting for LMCache server healthcheck. Log follows:" >&2
kill "$tail_pid" 2>/dev/null || true
wait "$tail_pid" 2>/dev/null || true
cat "$LMCACHE_LOG" >&2 || true
exit 1
}

case "$KV_OFFLOAD_BACKEND" in
native)
unset VLLM_USE_SIMPLE_KV_OFFLOAD
# Use vLLM's regular native KV-offload path (OffloadingConnector),
# NOT the SimpleCPUOffloadConnector. The "native" backend resolves to
# OffloadingConnector by default; setting VLLM_USE_SIMPLE_KV_OFFLOAD=1
# would switch it to SimpleCPUOffloadConnector. We intentionally leave
# that env var UNSET here so the regular OffloadingConnector path is
# used. The shortcut --kv_offloading_backend native + --kv_offloading_size
# form constructs the KVTransferConfig at engine startup
# (vllm/config/vllm.py:662).

# Remove --disable-hybrid-kv-cache-manager and enable hybrid kv cache manager (default)
# This gives extra cache hit than disabling hybrid kv cache manager
OFFLOAD_ARGS=(
--kv_offloading_backend native
--kv_offloading_size "$TOTAL_CPU_DRAM_GB"
)
;;
lmcache)
unset VLLM_USE_SIMPLE_KV_OFFLOAD

git clone https://github.com/LMCache/LMCache.git
cd LMCache
pip install -r requirements/build.txt
CXX=hipcc BUILD_WITH_HIP=1 pip install -e . --no-build-isolation
cd ..

python3 -c "import lmcache.integration.vllm.lmcache_mp_connector" >/dev/null

# Let the external MP server own the full CPU KV pool so vLLM does not
# split --kv-offloading-size across TP ranks through the integrated
# LMCache backend.
LMCACHE_HOST=127.0.0.1
LMCACHE_PORT=5555
LMCACHE_HTTP_PORT=8080
# LMCacheMPConnector concatenates lmcache.mp.host and port into the
# ZMQ endpoint. Bind the server to a raw host, but pass the connector a
# ZMQ-style host string.
LMCACHE_CONNECT_HOST="tcp://$LMCACHE_HOST"
LMCACHE_L1_SIZE_GB="$TOTAL_CPU_DRAM_GB"
LMCACHE_L1_INIT_SIZE_GB=20
# LMCache read locks are leases on chunks that lookup has promised
# vLLM can retrieve. The default 300s TTL is too short for this
# long-context agentic queue: TP8/conc32 can spend >300s between
# lookup and retrieve while GPU KV is saturated, which leaves the
# object present in L1 but no longer readable. Keep the 2.5 TB pool
# size unchanged and only extend the lookup-to-retrieve lease.
LMCACHE_L1_READ_TTL_SECONDS=7200
LMCACHE_CHUNK_SIZE=256
LMCACHE_MAX_WORKERS=$((TP * 2))
export PYTHONHASHSEED=0
export LMCACHE_BLOCKING_TIMEOUT_SECS=60

echo "Starting LMCache MP server..."
LMCACHE_CMD=(
lmcache server
--host "$LMCACHE_HOST"
--port "$LMCACHE_PORT"
--http-host "$LMCACHE_HOST"
--http-port "$LMCACHE_HTTP_PORT"
--l1-size-gb "$LMCACHE_L1_SIZE_GB"
--l1-init-size-gb "$LMCACHE_L1_INIT_SIZE_GB"
--l1-read-ttl-seconds "$LMCACHE_L1_READ_TTL_SECONDS"
--chunk-size "$LMCACHE_CHUNK_SIZE"
--max-workers "$LMCACHE_MAX_WORKERS"
--eviction-policy LRU
)
printf '%q ' "${LMCACHE_CMD[@]}" > "$RESULT_DIR/lmcache_command.txt"
printf '\n' >> "$RESULT_DIR/lmcache_command.txt"
"${LMCACHE_CMD[@]}" > "$LMCACHE_LOG" 2>&1 &
LMCACHE_PID=$!
echo "LMCache server PID: $LMCACHE_PID"
wait_for_lmcache_ready

# Remove --disable-hybrid-kv-cache-manager and enable hybrid kv cache manager (default)
# This gives extra cache hit than disabling hybrid kv cache manager
OFFLOAD_ARGS=(
--kv-transfer-config
"{\"kv_connector\":\"LMCacheMPConnector\",\"kv_connector_module_path\":\"lmcache.integration.vllm.lmcache_mp_connector\",\"kv_role\":\"kv_both\",\"kv_connector_extra_config\":{\"lmcache.mp.host\":\"$LMCACHE_CONNECT_HOST\",\"lmcache.mp.port\":$LMCACHE_PORT}}"
)
;;
esac

# ---- LLM server config ----------------------------------------------------------
PARALLEL_ARGS=(--tensor-parallel-size "$TP")
if [ "${DP_ATTENTION}" = "true" ]; then
PARALLEL_ARGS=(
--tensor-parallel-size 1
--data-parallel-size "$TP"
--enable-expert-parallel
)
elif [ "$EP_SIZE" -gt 1 ]; then
PARALLEL_ARGS+=(--enable-expert-parallel)
fi

echo "Starting vllm server..."
export PYTHONNOUSERSITE=1

export VLLM_ENGINE_READY_TIMEOUT_S=3600
export VLLM_USE_BREAKABLE_CUDAGRAPH=0
export VLLM_ROCM_USE_AITER=1
export VLLM_ROCM_USE_AITER_MOE=1
export VLLM_ROCM_USE_AITER_FUSION_SHARED_EXPERTS=1
# INT4 quantized all-reduce for the (~1.5 MB) decode all-reduces, which are the
# single biggest decode kernel at high concurrency. The MIN_SIZE_KB override is
# required: vLLM's default INT4 quick-reduce size gate for (bf16, TP4) is 16 MB,
# so it never fires for decode-sized tensors without it.
export VLLM_ROCM_QUICK_REDUCE_QUANTIZATION=INT4
export VLLM_ROCM_QUICK_REDUCE_CAST_BF16_TO_FP16=0
export VLLM_ROCM_QUICK_REDUCE_QUANTIZATION_MIN_SIZE_KB=256

VLLM_CMD=(
vllm serve "$MODEL_PATH"
--served-model-name "$MODEL"
--host 0.0.0.0
--port "$PORT"
"${PARALLEL_ARGS[@]}"
--trust-remote-code
--block-size 128
--gpu-memory-utilization 0.85
--language-model-only
--attention-backend TRITON_ATTN
--moe-backend aiter
--kv-cache-dtype fp8
--tool-call-parser minimax_m3
--enable-auto-tool-choice
--reasoning-parser minimax_m3
--max-num-seqs "$CONC"
"${OFFLOAD_ARGS[@]}"
)
Comment thread
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printf '%q ' "${VLLM_CMD[@]}" | tee "$RESULT_DIR/vllm_command.txt"
printf '\n' | tee -a "$RESULT_DIR/vllm_command.txt"
"${VLLM_CMD[@]}" > "$SERVER_LOG" 2>&1 &
SERVER_PID=$!
echo "Server PID: $SERVER_PID"

wait_for_server_ready --port "$PORT" --server-log "$SERVER_LOG" --server-pid "$SERVER_PID"

# ---- Run benchmark ----------------------------------------------------------
build_replay_cmd "$RESULT_DIR"

run_agentic_replay_and_write_outputs "$RESULT_DIR"
15 changes: 15 additions & 0 deletions configs/amd-master.yaml
Original file line number Diff line number Diff line change
Expand Up @@ -3123,6 +3123,21 @@ minimaxm3-fp8-mi325x-vllm-agentic:
- { tp: 8, ep: 8, kv-offloading: dram, kv-offload-backend: native, conc-list: [10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 32] }
- { tp: 8, ep: 8, dp-attn: true, kv-offloading: dram, kv-offload-backend: native, conc-list: [24, 32, 36, 40, 44, 48, 52, 56, 60, 64, 72, 80, 96] }

minimaxm3-fp4-mi355x-vllm-agentic:
image: vllm/vllm-openai-rocm:nightly-69715823df89b11ee684b84066390cbb9092d5c1
model: amd/MiniMax-M3-MXFP4
model-prefix: minimaxm3
runner: cluster:mi355x-amds
precision: fp4
framework: vllm
multinode: false
scenarios:
agentic-coding:
- dram-utilization: 0.80
search-space:
- { tp: 4, kv-offloading: dram, kv-offload-backend: lmcache, conc-list: [1, 4] }
- { tp: 4, kv-offloading: dram, kv-offload-backend: native, conc-list: [8, 16, 32] }

dsv4-fp4-mi355x-sglang-disagg-agentic-hicache:
image: lmsysorg/sglang-rocm:v0.5.14-rocm720-mi35x-20260710
model: deepseek-ai/DeepSeek-V4-Pro
Expand Down
7 changes: 7 additions & 0 deletions perf-changelog.yaml
Original file line number Diff line number Diff line change
Expand Up @@ -4627,6 +4627,13 @@
- "14 topologies across 1k/1k and 8k/1k: prefill TP8 STP + decode wide-EP (DEP16/DEP32 high-throughput) and per-node TP8 low-latency, recipes under benchmarks/multi_node/srt-slurm-recipes/sglang/glm5/gb200-fp8/"
pr-link: https://github.com/SemiAnalysisAI/InferenceX/pull/1895

- config-keys:
- minimaxm3-fp4-mi355x-vllm-agentic
description:
- "Add Minimax-M3 FP4 vLLM Single Node Agentic Support"
- "Image: vllm/vllm-openai-rocm:nightly-69715823df89b11ee684b84066390cbb9092d5c1"
pr-link: https://github.com/SemiAnalysisAI/InferenceX/pull/2118

- config-keys:
- glm5-fp4-gb200-dynamo-sglang
description:
Expand Down
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