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Quil180/README.md

Hi, I'm Yousef Awad ๐Ÿ‘‹

About Me

I'm a hardware design enthusiast passionate about digital design, FPGA development, and formal verification.

๐Ÿ”ญ Currently Working On

  • Digital design projects using Verilog and SystemVerilog
  • FPGA development and verification
  • Learning formal verification methods

๐Ÿ› ๏ธ Technologies & Tools

SystemVerilog Verilog Vivado Cadence Verilator Formal Verification UVM/OVM Constrained Randomized Tests C/C++ Rust

๐Ÿ“ซ How to Reach Me

LinkedIn Email

๐Ÿ“Š GitHub Stats (incase you are interested)

Quil180's GitHub stats

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  1. IEEE-UCF/2025-AMDHardware IEEE-UCF/2025-AMDHardware Public

    Python 1

  2. formal_verification_practice formal_verification_practice Public

    Verilog

  3. CyndaQuilLanguage CyndaQuilLanguage Public

    CyndaQuil is a statically-typed, compiled programming language focused on high performance, memory safety, and modern syntax. It features structured exception handling, strict grammar rules, and efโ€ฆ

    C++ 3

  4. Anqa Anqa Public

    Anqa is a personal RISC-V processor project focused on high-performance design with full documentation to help you build your own. Featuring modular extensions, an optimized ALU, and a structured pโ€ฆ

    TeX 1

  5. peytonlynnbarnes/sec_bot peytonlynnbarnes/sec_bot Public

    Python 2 1