UNIVERSITY OF WEST ATTICA
SCHOOL OF ENGINEERING
DEPARTMENT OF COMPUTER ENGINEERING AND INFORMATICS
University of West Attica · Department of Computer Engineering and Informatics
Logic Design
Vasileios Evangelos Athanasiou
Student ID: 19390005
Supervision
Supervisor: Konstantinos Efstathiou, Professor
Supervisor: Ioannis Amorginos, Applications Lecturer
Co-supervisor: Eleni Tsalera, Academic Scholar
Co-supervisor: Anastasios Tsilikounas, Laboratory Teaching Staff
Athens, June 2021
This repository contains the documentation and circuit simulations for Workshop 3 of the Digital Design course at the University of West Attica. The project focuses on the operation and implementation of sequential logic circuits, specifically latches and flip-flops.
| Section | Folder/File | Description |
|---|---|---|
| 1 | assign/ |
Assignment material for the Flip-Flops workshop |
| 1.1 | assign/ASSIGNMENT 3.pdf |
Assignment description in English |
| 1.2 | assign/ΕΡΓΑΣΙΑ 3.pdf |
Assignment description in Greek |
| 2 | docs/ |
Documentation covering flip-flops theory and memory states |
| 2.1 | docs/Flip-Flops.pdf |
English documentation for flip-flops |
| 2.2 | docs/Κατάσταση-Μνήμης.pdf |
Greek documentation for flip-flops and memory states |
| 3 | multisim/ |
Multisim flip-flop and counter simulation files |
| 3.1 | multisim/D-Flip-Flop.ms14 |
D Flip-Flop circuit simulation |
| 3.2 | multisim/RS-Flip-Flop.ms14 |
RS Flip-Flop circuit simulation |
| 3.3 | multisim/counter.ms14 |
Counter circuit simulation |
| 3.4 | multisim/pentagon-with-NAND.ms14 |
Pentagon sequence generator using NAND gates |
| 4 | README.md |
Project documentation |
| 5 | INSTALL.md |
Usage instructions |
The objective of this workshop is to explore the fundamental behavior of sequential circuits through theoretical analysis and software simulation.
- Latches: NAND and NOR gate implementations
- Flip-Flops: RS, D, JK, T, and Master-Slave configurations
- Operational Features: Excitation tables, asynchronous inputs, and clock triggering
- NI Multisim for circuit design, simulation, and testing
- Logic Gates: AND, OR, NOR, NAND, XOR, XNOR, NOT
- Hardware Elements: VCC sources (5V), ground, cables, switches
- Monitoring Tools: Logic lamps and oscilloscopes for signal visualization
Analyzes the truth table of a basic cross-coupled NAND gate latch.
| S | R | Q | NOT_Q | Result Description |
|---|---|---|---|---|
| 0 | 0 | 0 | 1 | Theoretical State |
| 1 | 0 | 1 | 1 | Invalid / Prohibited |
| 0 | 1 | 0 | 1 | Reset State |
| 1 | 1 | 1 | 0 | Set State |
Analysis of a clocked RS Flip-Flop implementation.
| S | R | Q | NOT_Q |
|---|---|---|---|
| 0 | 0 | 1 | 0 |
| 1 | 0 | ? | ? |
| 0 | 1 | 1 | 1 |
| 1 | 1 | 0 | 1 |
Note: Detailed simulation captures for each input combination (S=0/R=0, S=1/R=0, etc.) are included in the documentation.
Workshop 3 emphasizes the behavior and design of sequential circuits, building a foundation for memory elements in digital systems and demonstrating how flip-flops can store and manipulate binary information reliably.