Interrupts Module Briefs and PLIC #41
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Meowcaroni
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Nov 17, 2025
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@gavinwiese Good work on your PR (pull request)! Please make sure to add comments to your code and review my comment on your code. You can then request me to review your PR again.
Majority of code implemented, still needs more work to fully integrate with bus
Initial timer interrupt logic implemented
Meowcaroni
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Dec 8, 2025
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| always_ff @(posedge clk_i) begin | ||
| if (!rst_ni) begin | ||
| mtime_o <= 16'd0; | ||
| mtimecmp <= 16'd0; | ||
| Timer_irq_o <= 1'b0; | ||
| msip <= 1'b0; |
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Functionality Issue: To match other subsystems, please treat rst_ni as an asynchronous (independent of clock) reset.
EX: always_ff @(posedge clk_i or negedge rst_ni)
Meowcaroni
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Dec 8, 2025
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| always_ff @(posedge clk_i) begin | ||
| if (!rst_ni) begin | ||
| priorities <= 0; | ||
| enable <= 0; | ||
| claim <= 0; | ||
| activeClaim <= 0; | ||
| plicComplete <= 0; | ||
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| cpu_read <= 0; | ||
| cpu_write <= 0; | ||
| cpu_wdata <= 0; | ||
| cpu_addr <= 0; | ||
| end | ||
| end |
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Functionality Issue: To match other subsystems, please treat rst_ni as an asynchronous (independent of clock) reset.
EX: always_ff @(negedge rst_ni)
Meowcaroni
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Dec 8, 2025
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Meowcaroni
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Looking good so far, just convert reset into an asynchronous signal
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Wrote both module briefs describing the PLIC and CLINT, as well an initial skeleton code for the plic.sv