Cleanup from iot devices panel

edg/abstract_parts/AbstractCapacitor.py

@@ -264,15 +264,16 @@ def add_derated_row(row: PartsTableRow) -> Optional[Dict[PartsTableColumn, Any]]
     ))
 
   def _row_generate(self, row: PartsTableRow) -> None:
+    """This one is weird. Because this is the last in the class order, this is called last.
+    So the top subclass needs explicit logic to handle parallel capacitors."""
+    super()._row_generate(row)
     if row[self.PARALLEL_COUNT] == 1:
-      super()._row_generate(row)  # creates the footprint
       self.assign(self.actual_derated_capacitance, row[self.DERATED_CAPACITANCE])
     else:
       self.assign(self.actual_part, f"{row[self.PARALLEL_COUNT]}x {row[self.PART_NUMBER_COL]}")
       self.assign(self.actual_voltage_rating, row[self.VOLTAGE_RATING])
       self.assign(self.actual_capacitance, row[self.PARALLEL_CAPACITANCE])
       self.assign(self.actual_derated_capacitance, row[self.PARALLEL_DERATED_CAPACITANCE])
-      self._make_parallel_footprints(row)
 
   @abstractmethod
   def _make_parallel_footprints(self, row: PartsTableRow) -> None:

edg/abstract_parts/AbstractComparator.py

@@ -1,9 +1,10 @@
 from typing import Mapping
 
+from ..abstract_parts import Analog
 from ..electronics_model import *
 
 
-class Comparator(KiCadInstantiableBlock, Block):
+class Comparator(KiCadInstantiableBlock, Analog):
     """Abstract comparator interface, output goes high when inp > inn."""
     def symbol_pinning(self, symbol_name: str) -> Mapping[str, BasePort]:
         assert symbol_name in ('Simulation_SPICE:OPAMP', 'edg_importable:Opamp')

edg/abstract_parts/AbstractFuse.py

@@ -1,5 +1,7 @@
 from typing import Optional, cast
 
+from deprecated import deprecated
+
 from ..electronics_model import *
 from .Categories import *
 from .PartsTable import PartsTableColumn, PartsTableRow
@@ -132,5 +134,6 @@ def _row_generate(self, row: PartsTableRow) -> None:
     self.assign(self.actual_voltage_rating, row[self.VOLTAGE_RATING])
 
 
+@deprecated("Use SeriesPowerFuse and a top-level refinement to specify a PPTC fuse")
 class SeriesPowerPptcFuse(SeriesPowerFuse):
   FUSE_TYPE = PptcFuse

edg/abstract_parts/AbstractLedDriver.py

@@ -1,4 +1,5 @@
 from ..abstract_parts import *
+from deprecated import deprecated
 
 
 @abstract_block
@@ -18,6 +19,7 @@ def __init__(self, max_current: RangeLike):
         self.max_current = self.ArgParameter(max_current)
 
 
+@deprecated("ripple should be an internal parameter")
 class LedDriverSwitchingConverter(BlockInterfaceMixin[LedDriver]):
     """LED driver mixin indicating that the LED driver is a switching converter and with a peak-peak ripple limit."""
     @init_in_parent

edg/abstract_parts/Categories.py

@@ -32,6 +32,12 @@ class AnalogFilter(Filter):
   pass
 
 
+@abstract_block
+class RfFilter(AnalogFilter):
+  """RF signal conditioning subcircuit."""
+  pass
+
+
 @abstract_block
 class DigitalFilter(Filter):
   """Digital signal conditioning block."""

edg/abstract_parts/I2cBitBang.py

@@ -6,19 +6,6 @@
 
 class I2cControllerBitBang(BitBangAdapter, Block):
   """Bit-bang adapter for I2C controller"""
-  @staticmethod
-  def digital_external_from_link(link_port: DigitalBidir) -> DigitalBidir:
-    """Creates a DigitalBidir model that is the external-facing port that exports from
-    an internal-facing (link-side) port. The internal-facing port should be ideal.
-    These are basically the semantics of a DigitalBidir bridge.
-    TODO: unify code w/ DigitalBidir bridge?"""
-    return DigitalBidir(
-      voltage_out=link_port.link().voltage, current_draw=link_port.link().current_drawn,
-      voltage_limits=link_port.link().voltage_limits, current_limits=link_port.link().current_limits,
-      output_thresholds=link_port.link().output_thresholds, input_thresholds=link_port.link().input_thresholds,
-      pulldown_capable=link_port.link().pulldown_capable, pullup_capable=link_port.link().pullup_capable
-    )
-
   def __init__(self) -> None:
     super().__init__()
     self.i2c = self.Port(I2cController.empty(), [Output])

edg/abstract_parts/IoController.py

@@ -8,6 +8,7 @@
 from .Categories import ProgrammableController
 
 
+@non_library
 @abstract_block
 class BaseIoController(PinMappable, Block):
   """An abstract IO controller block, that takes power input and provides a grab-bag of common IOs.

edg/abstract_parts/RfNetworks.py

@@ -56,7 +56,7 @@ def _calculate_values(cls, freq: float, z1: complex, z2: complex) -> Tuple[float
             PiLowPassFilter._reactance_to_capacitance(freq, xp)
 
 
-class LLowPassFilterWith2HNotch(AnalogFilter, GeneratorBlock):
+class LLowPassFilterWith2HNotch(GeneratorBlock, RfFilter):
     """L filter for impedance matching for RF with an overlaid second-harmonic LC notch filter.
     The target reactance is given by the L filter.
     Then, the L and C values are from the simultaneous solution of:
@@ -143,7 +143,7 @@ def _calculate_values(cls, freq: float, z1: complex, z2: complex) -> Tuple[float
             PiLowPassFilter._reactance_to_capacitance(freq, net_xs - xs2)
 
 
-class PiLowPassFilter(AnalogFilter, GeneratorBlock):
+class PiLowPassFilter(GeneratorBlock, RfFilter):
     """Passive-typed pi impedance matching network.
     Based on equations from https://www.silabs.com/documents/public/application-notes/an1275-imp-match-for-network-arch.pdf
     and also referencing https://www.electronicdesign.com/technologies/communications/article/21801154/back-to-basics-impedance-matching-part-3

edg/abstract_parts/__init__.py

@@ -9,7 +9,7 @@
 from .Categories import DiscreteComponent, DiscreteSemiconductor, PassiveComponent
 from .Categories import DiscreteApplication
 from .Categories import Analog, OpampApplication
-from .Categories import Filter, AnalogFilter, DigitalFilter
+from .Categories import Filter, AnalogFilter, RfFilter, DigitalFilter
 from .Categories import Microcontroller, Fpga, Memory, RealtimeClock, Radiofrequency
 from .Categories import Interface, AnalogToDigital, DigitalToAnalog, SpeakerDriver, IoExpander, BitBangAdapter
 from .Categories import PowerConditioner, PowerSwitch, MotorDriver, BrushedMotorDriver, BldcDriver

edg/electronics_model/CircuitBlock.py

@@ -91,6 +91,7 @@ def footprint(self, refdes: StringLike, footprint: StringLike, pinning: Mapping[
       self.assign(self.fp_datasheet, '')
 
 
+@non_library
 class WrapperFootprintBlock(FootprintBlock):
   """Block that has a footprint and optional internal contents, but the netlister ignores internal components.
   Useful for, for example, a breakout board where the modelling details are provided by internal chip blocks,

edg/jlcparts/JlcPartsBjt.py

@@ -4,7 +4,7 @@
 from .JlcPartsBase import JlcPartsBase, JlcPartsAttributes
 
 
-class JlcPartsBjt(TableBjt, PartsTableSelectorFootprint, JlcPartsBase):
+class JlcPartsBjt(PartsTableSelectorFootprint, JlcPartsBase, TableBjt):
     _JLC_PARTS_FILE_NAMES = ["TransistorsBipolar_Transistors___BJT"]
     _CHANNEL_MAP = {
         'NPN': 'NPN',

edg/jlcparts/JlcPartsDiode.py

@@ -4,7 +4,7 @@
 from .JlcPartsBase import JlcPartsBase, JlcPartsAttributes
 
 
-class JlcPartsDiode(TableDiode, PartsTableSelectorFootprint, JlcPartsBase):
+class JlcPartsDiode(PartsTableSelectorFootprint, JlcPartsBase, TableDiode):
     _JLC_PARTS_FILE_NAMES = [
         "DiodesSchottky_Barrier_Diodes__SBD_",
         "DiodesDiodes___Fast_Recovery_Rectifiers",

edg/jlcparts/JlcPartsElectrolyticCapacitor.py

@@ -4,7 +4,7 @@
 from .JlcPartsBase import JlcPartsBase, JlcPartsAttributes
 
 
-class JlcPartsElectrolyticCapacitor(TableCapacitor, AluminumCapacitor, PartsTableSelectorFootprint, JlcPartsBase):
+class JlcPartsElectrolyticCapacitor(PartsTableSelectorFootprint, JlcPartsBase, TableCapacitor, AluminumCapacitor):
     _JLC_PARTS_FILE_NAMES = ["CapacitorsAluminum_Electrolytic_Capacitors___SMD"]
     _PACKAGE_PARSER = re.compile(r"^SMD,D([\d.]+)xL([\d.]+)mm$")
 

edg/jlcparts/JlcPartsFerriteBead.py

@@ -4,7 +4,7 @@
 from .JlcPartsBase import JlcPartsBase, JlcPartsAttributes
 
 
-class JlcPartsFerriteBead(TableFerriteBead, PartsTableSelectorFootprint, JlcPartsBase):
+class JlcPartsFerriteBead(PartsTableSelectorFootprint, JlcPartsBase, TableFerriteBead):
     _JLC_PARTS_FILE_NAMES = ["FiltersakaEMI_OptimizationFerrite_Beads"]
 
     @classmethod

edg/jlcparts/JlcPartsFet.py

@@ -53,11 +53,11 @@ def _entry_to_table_row(cls, row_dict: Dict[PartsTableColumn, Any], filename: st
             return None
 
 
-class JlcPartsFet(TableFet, PartsTableSelectorFootprint, JlcPartsBaseFet):
+class JlcPartsFet(PartsTableSelectorFootprint, JlcPartsBaseFet, TableFet):
     pass
 
 
-class JlcPartsSwitchFet(TableSwitchFet, PartsTableSelectorFootprint, JlcPartsBaseFet):
+class JlcPartsSwitchFet(PartsTableSelectorFootprint, JlcPartsBaseFet, TableSwitchFet):
     @init_in_parent
     def __init__(self, *args, manual_gate_charge: RangeLike = RangeExpr.ZERO, **kwargs):
         super().__init__(*args, **kwargs)

edg/jlcparts/JlcPartsLed.py

@@ -4,7 +4,7 @@
 from .JlcPartsBase import JlcPartsBase, JlcPartsAttributes
 
 
-class JlcPartsLed(TableLed, PartsTableSelectorFootprint, JlcPartsBase):
+class JlcPartsLed(PartsTableSelectorFootprint, JlcPartsBase, TableLed):
     _JLC_PARTS_FILE_NAMES = [
         "OptoelectronicsLight_Emitting_Diodes__LED_",
         "OptoelectronicsLED_Indication___Discrete",

edg/jlcparts/JlcPartsMlcc.py

@@ -4,7 +4,7 @@
 from .JlcPartsBase import JlcPartsBase, JlcPartsAttributes
 
 
-class JlcPartsMlcc(TableDeratingCapacitor, CeramicCapacitor, PartsTableSelectorFootprint, JlcPartsBase):
+class JlcPartsMlcc(PartsTableSelectorFootprint, JlcPartsBase, TableDeratingCapacitor, CeramicCapacitor):
     _JLC_PARTS_FILE_NAMES = ["CapacitorsMultilayer_Ceramic_Capacitors_MLCC___SMDakaSMT"]
 
     @init_in_parent
@@ -63,6 +63,15 @@ def filter_minimum_size(row: PartsTableRow) -> Optional[Dict[PartsTableColumn, A
     def _row_sort_by(cls, row: PartsTableRow) -> Any:
         return [row[cls.PARALLEL_COUNT], super(JlcPartsMlcc, cls)._row_sort_by(row)]
 
+    def _row_generate(self, row: PartsTableRow) -> None:
+        # see comment in TableCapacitor._row_generate for why this needs to be here
+        if row[self.PARALLEL_COUNT] == 1:
+            super()._row_generate(row)  # creates the footprint
+        else:
+            TableCapacitor._row_generate(self, row)  # skips creating the footprint in PartsTableSelectorFootprint
+            self.assign(self.actual_basic_part, True)  # dummy value
+            self._make_parallel_footprints(row)
+
     def _make_parallel_footprints(self, row: PartsTableRow) -> None:
         cap_model = JlcDummyCapacitor(set_lcsc_part=row[self.LCSC_COL],
                                       set_basic_part=row[self.BASIC_PART_COL],
@@ -77,8 +86,5 @@ def _make_parallel_footprints(self, row: PartsTableRow) -> None:
             self.connect(self.c[i].pos, self.pos)
             self.connect(self.c[i].neg, self.neg)
 
-        self.assign(self.lcsc_part, row[self.LCSC_COL])
-        self.assign(self.actual_basic_part, row[self.BASIC_PART_COL])
-
 
 lambda: JlcPartsMlcc()  # ensure class is instantiable (non-abstract)

edg/jlcparts/JlcPartsPptcFuse.py

@@ -4,7 +4,7 @@
 from .JlcPartsBase import JlcPartsBase, JlcPartsAttributes
 
 
-class JlcPartsPptcFuse(TableFuse, PptcFuse, PartsTableSelectorFootprint, JlcPartsBase):
+class JlcPartsPptcFuse(PartsTableSelectorFootprint, JlcPartsBase, TableFuse, PptcFuse):
     _JLC_PARTS_FILE_NAMES = ["Circuit_ProtectionResettable_Fuses"]
 
     @classmethod

edg/jlcparts/JlcPartsResistorSmd.py

@@ -4,7 +4,7 @@
 from .JlcPartsBase import JlcPartsBase, JlcPartsAttributes
 
 
-class JlcPartsResistorSmd(TableResistor, PartsTableSelectorFootprint, JlcPartsBase):
+class JlcPartsResistorSmd(PartsTableSelectorFootprint, JlcPartsBase, TableResistor):
     _JLC_PARTS_FILE_NAMES = ["ResistorsChip_Resistor___Surface_Mount"]
 
     @classmethod

edg/parts/JlcAntenna.py

@@ -4,7 +4,7 @@
 from .JlcPart import JlcTableSelector
 
 
-class JlcAntenna(TableAntenna, JlcTableSelector, FootprintBlock):
+class JlcAntenna(JlcTableSelector, TableAntenna, FootprintBlock):
   # abstract Antenna does not define standard footprints, so we cannot mix in PartsTableSelectorFootprint
   # to do footprint generation
 

edg/parts/JlcBjt.py

@@ -5,7 +5,7 @@
 from .JlcPart import DescriptionParser, JlcTableSelector
 
 
-class JlcBjt(TableBjt, PartsTableSelectorFootprint, JlcTableSelector):
+class JlcBjt(PartsTableSelectorFootprint, JlcTableSelector, TableBjt):
   PACKAGE_FOOTPRINT_MAP = {
     'SOT-23': 'Package_TO_SOT_SMD:SOT-23',
     'SOT-23-3': 'Package_TO_SOT_SMD:SOT-23',

edg/parts/JlcCapacitor.py

@@ -5,7 +5,7 @@
 from .JlcPart import JlcPart, JlcTableSelector
 
 
-class JlcCapacitor(TableDeratingCapacitor, CeramicCapacitor, PartsTableSelectorFootprint, JlcTableSelector):
+class JlcCapacitor(JlcTableSelector, PartsTableSelectorFootprint, TableDeratingCapacitor, CeramicCapacitor):
   PACKAGE_FOOTPRINT_MAP = {
     '0201': 'Capacitor_SMD:C_0201_0603Metric',
     '0402': 'Capacitor_SMD:C_0402_1005Metric',
@@ -104,6 +104,15 @@ def filter_minimum_size(row: PartsTableRow) -> Optional[Dict[PartsTableColumn, A
   def _row_sort_by(cls, row: PartsTableRow) -> Any:
     return [row[cls.PARALLEL_COUNT], super(JlcCapacitor, cls)._row_sort_by(row)]
 
+  def _row_generate(self, row: PartsTableRow) -> None:
+    # see comment in TableCapacitor._row_generate for why this needs to be here
+    if row[self.PARALLEL_COUNT] == 1:
+      super()._row_generate(row)  # creates the footprint
+    else:
+      TableCapacitor._row_generate(self, row)  # skips creating the footprint in PartsTableSelectorFootprint
+      self.assign(self.actual_basic_part, True)  # dummy value
+      self._make_parallel_footprints(row)
+
   def _make_parallel_footprints(self, row: PartsTableRow) -> None:
     cap_model = JlcDummyCapacitor(set_lcsc_part=row[self.LCSC_PART_HEADER],
                                   set_basic_part=row[self.BASIC_PART_HEADER] == self.BASIC_PART_VALUE,
@@ -118,18 +127,16 @@ def _make_parallel_footprints(self, row: PartsTableRow) -> None:
       self.connect(self.c[i].pos, self.pos)
       self.connect(self.c[i].neg, self.neg)
 
-    self.assign(self.lcsc_part, row[self.LCSC_PART_HEADER])
-    self.assign(self.actual_basic_part, row[self.BASIC_PART_HEADER] == self.BASIC_PART_VALUE)
-
 
-class JlcDummyCapacitor(DummyCapacitorFootprint, JlcPart):
+class JlcDummyCapacitor(JlcPart, DummyCapacitorFootprint):
   """Dummy capacitor that additionally has JLC part fields
   """
   @init_in_parent
   def __init__(self, set_lcsc_part: StringLike = "", set_basic_part: BoolLike = False,
                footprint: StringLike = "", manufacturer: StringLike = "",
                part_number: StringLike = "", value: StringLike = "", *args, **kwargs) -> None:
-    super().__init__(footprint, manufacturer, part_number, value, *args, **kwargs)
+    super().__init__(footprint=footprint, manufacturer=manufacturer, part_number=part_number,
+                     value=value, *args, **kwargs)
 
     self.assign(self.lcsc_part, set_lcsc_part)
     self.assign(self.actual_basic_part, set_basic_part)

edg/parts/JlcCrystal.py

@@ -4,7 +4,7 @@
 from .JlcPart import JlcTableSelector, DescriptionParser
 
 
-class JlcCrystal(TableCrystal, PartsTableSelectorFootprint, JlcTableSelector):
+class JlcCrystal(PartsTableSelectorFootprint, JlcTableSelector, TableCrystal):
   SERIES_PACKAGE_FOOTPRINT_MAP = {
     ('X3225', 'SMD-3225_4P'): 'Crystal:Crystal_SMD_3225-4Pin_3.2x2.5mm',
     ('TXM', 'SMD-2520_4P'): 'Crystal:Crystal_SMD_2520-4Pin_2.5x2.0mm',

edg/parts/JlcDiode.py

@@ -18,7 +18,7 @@ class JlcBaseDiode:
   }
 
 
-class JlcDiode(TableDiode, PartsTableSelectorFootprint, JlcTableSelector, JlcBaseDiode):
+class JlcDiode(PartsTableSelectorFootprint, JlcTableSelector, JlcBaseDiode, TableDiode):
   DESCRIPTION_PARSERS: List[DescriptionParser] = [
     (re.compile("(\S+V) (\S+V)@\S+A (\S+A) .* Schottky Barrier Diodes \(SBD\).*"),
      lambda match: {
@@ -75,7 +75,7 @@ def parse_row(row: PartsTableRow) -> Optional[Dict[PartsTableColumn, Any]]:
     return cls._jlc_table().map_new_columns(parse_row)
 
 
-class JlcZenerDiode(TableZenerDiode, PartsTableSelectorFootprint, JlcTableSelector, JlcBaseDiode):
+class JlcZenerDiode(PartsTableSelectorFootprint, JlcTableSelector, JlcBaseDiode, TableZenerDiode):
   DESCRIPTION_PARSERS: List[DescriptionParser] = [
     (re.compile("\S+A@\S+V (±\S+%) \S+Ω (?:Single )?(\S+W) (\S+V).* Zener Diodes.*"),
      lambda match: {

edg/parts/JlcElectrolyticCapacitor.py

@@ -5,7 +5,7 @@
 from .JlcPart import DescriptionParser, JlcTableSelector
 
 
-class JlcAluminumCapacitor(TableCapacitor, AluminumCapacitor, PartsTableSelectorFootprint, JlcTableSelector):
+class JlcAluminumCapacitor(PartsTableSelectorFootprint, JlcTableSelector, TableCapacitor, AluminumCapacitor):
   DESCRIPTION_PARSERS: List[DescriptionParser] = [
     (re.compile(".* (\S+F).* (\S+V).* (±\S+%).*([\d\.]+x[\d\.]+)mm Aluminum Electrolytic Capacitors.*"),
      lambda match: {  # discard the HF impedance parameter

edg/parts/JlcFerriteBead.py

@@ -5,7 +5,7 @@
 from .JlcPart import DescriptionParser, JlcTableSelector
 
 
-class JlcFerriteBead(TableFerriteBead, PartsTableSelectorFootprint, JlcTableSelector):
+class JlcFerriteBead(PartsTableSelectorFootprint, JlcTableSelector, TableFerriteBead):
   PACKAGE_FOOTPRINT_MAP = {
     '0402': 'Inductor_SMD:L_0402_1005Metric',
     '0603': 'Inductor_SMD:L_0603_1608Metric',

edg/parts/JlcFet.py

@@ -80,11 +80,11 @@ def parse_row(row: PartsTableRow) -> Optional[Dict[PartsTableColumn, Any]]:
     return cls._jlc_table().map_new_columns(parse_row)
 
 
-class JlcFet(TableFet, PartsTableSelectorFootprint, JlcBaseFet):
+class JlcFet(PartsTableSelectorFootprint, JlcBaseFet, TableFet):
   pass
 
 
-class JlcSwitchFet(TableSwitchFet, PartsTableSelectorFootprint, JlcBaseFet):
+class JlcSwitchFet(PartsTableSelectorFootprint, JlcBaseFet, TableSwitchFet):
   @init_in_parent
   def __init__(self, *args, manual_gate_charge: RangeLike = RangeExpr.ZERO, **kwargs):
     super().__init__(*args, **kwargs)

edg/parts/JlcLed.py

@@ -4,7 +4,7 @@
 from .JlcPart import JlcTableSelector
 
 
-class JlcLed(TableLed, PartsTableSelectorFootprint, JlcTableSelector):
+class JlcLed(PartsTableSelectorFootprint, JlcTableSelector, TableLed):
   PACKAGE_FOOTPRINT_MAP = {
     # 0201 not in parts table, LED_0201_0603Metric
 

edg/parts/JlcOscillator.py

@@ -60,7 +60,7 @@ class Sg8101ce_Device(Sg8101_Base_Device):
   FOOTPRINT = 'Crystal:Crystal_SMD_3225-4Pin_3.2x2.5mm'  # doesn't perfectly match datasheet recommended geometry
 
 
-class JlcOscillator(TableOscillator, JlcTableSelector):
+class JlcOscillator(JlcTableSelector, TableOscillator):
   SERIES_DEVICE_MAP = {
     'SG-8101CG': Sg8101cg_Device,
     'SG-8101CE': Sg8101ce_Device,

edg/parts/JlcPptcFuse.py

@@ -5,7 +5,7 @@
 from .JlcPart import DescriptionParser, JlcTableSelector
 
 
-class JlcPptcFuse(TableFuse, PptcFuse, PartsTableSelectorFootprint, JlcTableSelector):
+class JlcPptcFuse(PartsTableSelectorFootprint, JlcTableSelector, TableFuse, PptcFuse):
   PACKAGE_FOOTPRINT_MAP = {
     '0402': 'Resistor_SMD:R_0402_1005Metric',
     '0603': 'Resistor_SMD:R_0603_1608Metric',