Skip to content

Fix SDRAM timing setup during initialization #457

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Open
pat-rogers wants to merge 1 commit into
base: master
Choose a base branch
from
Open

Fix SDRAM timing setup during initialization #457

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
28 changes: 11 additions & 17 deletions boards/stm32_common/sdram/stm32-sdram.adb
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
------------------------------------------------------------------------------
-- --
-- Copyright (C) 2015-2016, AdaCore --
-- Copyright (C) 2015-2026, AdaCore --
-- --
-- Redistribution and use in source and binary forms, with or without --
-- modification, are permitted provided that the following conditions are --
Expand Down Expand Up @@ -141,9 +141,7 @@ package body STM32.SDRAM is
SDRAM_Conf : FMC_SDRAM_Init_Config;
SDCLK : constant Unsigned_32 :=
Unsigned_32 (STM32.Device.System_Clock_Frequencies.SYSCLK / 2);
SDPeriod_In_ns : constant Unsigned_32 :=
1_000_000_000 / SDCLK;
Refresh_Delay : Unsigned_32;
SDPeriod_In_Ns : constant Unsigned_32 := 1_000_000_000 / SDCLK;

begin
if Initialized then
Expand Down Expand Up @@ -171,22 +169,19 @@ package body STM32.SDRAM is
-- 100 MHz of SD clock frequency (200MHz / 2)
-- 1 Clock cycle = 1 / 100MHz = 10ns

Refresh_Delay :=
(SDRAM_Min_Delay_In_ns - SDPeriod_In_ns + 1) / SDPeriod_In_ns;

Timing_Conf :=
(
-- 2 Clock cycles for Load to Active delay
LoadToActiveDelay => 2,

-- min = 60ns: 6 * 10.0
ExitSelfRefreshDelay => FMC_SDRAM_Timing (Refresh_Delay),

-- in range [42ns, 120k ns] => using 4 * 11.1 ns
SelfRefreshTime => 4,

-- min = 60ns
RowCycleDelay => FMC_SDRAM_Timing (Refresh_Delay),
-- Each timing parameter is computed as a cycle count by dividing the
-- required minimum time (in ns) by the SDCLK period, using ceiling
-- division to ensure the minimum is always satisfied regardless of
-- clock frequency. The timing constants are defined in STM32.Board
-- and reflect the IS42S32400F SDRAM datasheet specifications.
ExitSelfRefreshDelay => FMC_SDRAM_Timing ((SDRAM_TXSR_In_Ns + SDPeriod_In_Ns - 1) / SDPeriod_In_Ns),
SelfRefreshTime => FMC_SDRAM_Timing ((SDRAM_TRAS_In_Ns + SDPeriod_In_Ns - 1) / SDPeriod_In_Ns),
RowCycleDelay => FMC_SDRAM_Timing ((SDRAM_TRC_In_Ns + SDPeriod_In_Ns - 1) / SDPeriod_In_Ns),

-- min = 20ns
WriteRecoveryTime => 2,
Expand Down Expand Up @@ -241,8 +236,7 @@ package body STM32.SDRAM is
begin
Initialize;
Rounded_Size := Amount + Align;
Rounded_Size :=
Rounded_Size - Rounded_Size rem Align;
Rounded_Size := Rounded_Size - Rounded_Size rem Align;

G_Base_Addr := G_Base_Addr + Rounded_Size;

Expand Down
6 changes: 4 additions & 2 deletions boards/stm32_common/stm32f746disco/stm32-board.ads
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
------------------------------------------------------------------------------
-- --
-- Copyright (C) 2015-2018, AdaCore --
-- Copyright (C) 2015-2026, AdaCore --
-- --
-- Redistribution and use in source and binary forms, with or without --
-- modification, are permitted provided that the following conditions are --
Expand Down Expand Up @@ -116,7 +116,9 @@ package STM32.Board is
SDRAM_Read_Pipe : constant STM32.FMC.FMC_SDRAM_Read_Pipe_Delay :=
STM32.FMC.FMC_ReadPipe_Delay_0;
SDRAM_Refresh_Cnt : constant := 1539;
SDRAM_Min_Delay_In_ns : constant := 60;
SDRAM_TRAS_In_Ns : constant := 42; -- IS42S32400F min self-refresh time
SDRAM_TRC_In_Ns : constant := 60; -- IS42S32400F min row cycle time
SDRAM_TXSR_In_Ns : constant := 70; -- IS42S32400F min exit self-refresh delay

---------
-- I2C --
Expand Down
Loading