Fix SDRAM timing setup during initialization#457
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pat-rogers wants to merge 1 commit intoAdaCore:masterfrom
Open
Fix SDRAM timing setup during initialization#457pat-rogers wants to merge 1 commit intoAdaCore:masterfrom
pat-rogers wants to merge 1 commit intoAdaCore:masterfrom
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We now compute them from the datasheet constants. Specifically, in procedure Initialize: * ExitSelfRefreshDelay, SelfRefreshTime, and RowCycleDelay were all derived from a single SDRAM_Min_Delay_In_ns constant, collapsing three distinct timing constraints (TXSR, TRAS, TRC) into one value. SelfRefreshTime was also hardcoded to 4 cycles, valid only at 90 MHz SDCLK. * Replace with per-parameter ceiling division over named board constants (SDRAM_TXSR_In_Ns, SDRAM_TRAS_In_Ns, SDRAM_TRC_In_Ns) so each constraint is satisfied independently at any clock frequency. STM32.Board spec: * add new SDRAM constants for the sake of the SDRAM initialization
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We now compute them from the datasheet constants.
Specifically, in procedure Initialize:
ExitSelfRefreshDelay, SelfRefreshTime, and RowCycleDelay were all derived from a single SDRAM_Min_Delay_In_ns constant, collapsing three distinct timing constraints (TXSR, TRAS, TRC) into one value.
SelfRefreshTime was also hardcoded to 4 cycles, valid only at 90 MHz SDCLK.
Replace with per-parameter ceiling division over named board constants (SDRAM_TXSR_In_Ns, SDRAM_TRAS_In_Ns, SDRAM_TRC_In_Ns) so each constraint is satisfied independently at any clock frequency.
STM32.Board spec: