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Fix: Mask shift amount to 5 bits for SLL, SRL, and SRA instructions #1

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Fix: Mask shift amount to 5 bits for SLL, SRL, and SRA instructions #1

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6 changes: 3 additions & 3 deletions hdl/alu.vhd
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Original file line number Diff line number Diff line change
Expand Up @@ -35,9 +35,9 @@ begin
and_w <= data1_i and data2_i;
or_w <= data1_i or data2_i;
xor_w <= data1_i xor data2_i;
sll_w <= std_logic_vector(shift_left(unsigned(data1_i), to_integer(unsigned(data2_i))));
srl_w <= std_logic_vector(shift_right(unsigned(data1_i), to_integer(unsigned(data2_i))));
sra_w <= std_logic_vector(shift_right(signed(data1_i), to_integer(unsigned(data2_i))));
sll_w <= std_logic_vector(shift_left(unsigned(data1_i), to_integer(unsigned(data2_i(4 downto 0)))));
srl_w <= std_logic_vector(shift_right(unsigned(data1_i), to_integer(unsigned(data2_i(4 downto 0)))));
sra_w <= std_logic_vector(shift_right(signed(data1_i), to_integer(unsigned(data2_i(4 downto 0)))));
slt_w <= (0 => '1', others => '0') when signed(data1_i) < signed(data2_i) else (others => '0');
sltu_w <= (0 => '1', others => '0') when unsigned(data1_i) < unsigned(data2_i) else (others => '0');

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