Add bare-metal wolfIP ports for ZCU102, Versal and Zynq-7000#121
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dgarske wants to merge 3 commits into
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Add bare-metal wolfIP ports for ZCU102, Versal and Zynq-7000#121dgarske wants to merge 3 commits into
dgarske wants to merge 3 commits into
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Pull request overview
Adds a new bare-metal AArch64 (Cortex-A53 EL3) wolfIP port targeting the Xilinx ZCU102 board, including a clean-room Cadence GEM3 + DP83867 PHY driver, minimal EL3 MMU/GIC/UART bring-up, and supporting JTAG/bootgen/SD tooling.
Changes:
- Introduces
src/port/zcu102/(startup vectors, MMU setup, GICv2 driver, polled UART, GEM3 Ethernet + DP83867 PHY, UDP echo + DHCP demo, build/link scripts). - Adds ZCU102 JTAG loader scripts (generic
tools/scripts/zcu102/and port-specificsrc/port/zcu102/jtag/). - Adds BOOT.BIN generation templates and an SD flashing helper.
Reviewed changes
Copilot reviewed 27 out of 27 changed files in this pull request and generated 16 comments.
Show a summary per file
| File | Description |
|---|---|
| tools/scripts/zcu102/README.md | Documents the generic ZCU102 xsdb loader pattern and constraints. |
| tools/scripts/zcu102/jtag_load.tcl | Generic xsdb JTAG loader for AArch64 EL3 apps (OCM load + RVBAR loop + entry jump). |
| src/port/zcu102/.gitignore | Ignores local build artifacts for the ZCU102 port. |
| src/port/zcu102/board.h | Board-specific base addresses/IRQs/clock/reset regs and default MAC. |
| src/port/zcu102/config.h | UDP-focused wolfIP configuration for the ZCU102 port. |
| src/port/zcu102/flash_sd.sh | Helper to copy BOOT.BIN to an SD boot partition with safety checks. |
| src/port/zcu102/gem.h | Public GEM3 + MDIO API surface for the port. |
| src/port/zcu102/gem.c | Clean-room GEM3 driver (BD rings, MDIO, polled RX/TX integration with wolfIP). |
| src/port/zcu102/gic.h | Minimal GICv2 interface and IRQ dispatch hooks. |
| src/port/zcu102/gic.c | GIC-400 bring-up and dispatch implementation (plus polled dispatch helper). |
| src/port/zcu102/jtag/boot.sh | Port-local wrapper to build a flat binary and invoke xsdb boot sequence. |
| src/port/zcu102/jtag/boot.tcl | Port-local xsdb sequence to init PS, load OCM, and run the app. |
| src/port/zcu102/jtag/boot_iter.sh | Developer iteration helper (power-cycle + hw_server restart + boot). |
| src/port/zcu102/main.c | Demo app (wolfIP init, DHCP, UDP echo) + wrapped memset/memcpy + exception reporting. |
| src/port/zcu102/mmu.h | Declares EL3 MMU enable entrypoint. |
| src/port/zcu102/mmu.c | Static EL3 page tables and MMU enable sequence (TCR/MAIR/TTBR setup). |
| src/port/zcu102/phy_dp83867.h | DP83867 PHY init/link-status API. |
| src/port/zcu102/phy_dp83867.c | DP83867 configuration (strap fix, delays, AN/link polling) via MDIO. |
| src/port/zcu102/README.md | Port-level documentation (features, build/boot workflow, expected output). |
| src/port/zcu102/startup.S | EL3 vectors + startup (BSS clear, MMU enable, IRQ trampoline, exception trampolines). |
| src/port/zcu102/target.ld | AArch64 linker script for OCM-based layout and special sections. |
| src/port/zcu102/timer.h | Generic timer-based delay utilities. |
| src/port/zcu102/uart.h | UART API for the port. |
| src/port/zcu102/uart.c | Polled Cadence UART0 driver and small print helpers. |
| src/port/zcu102/bootgen/boot.bif | BOOT.BIN template for bootgen. |
| src/port/zcu102/bootgen/build_bootbin.sh | Script to render the BIF template and run bootgen. |
| src/port/zcu102/Makefile | Port-local build (app.elf + BOOT.BIN) and core compilation strategy. |
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Single A53 at EL3, no Xilinx BSP/FreeRTOS: clean-room Cadence GEM3 driver + TI DP83867 RGMII at 1 Gbps, IRQ-driven RX via GIC-400, EL3 MMU/caches, PS-UART0 console, DHCP client and UDP echo (port 7). Boots via stock FSBL from an SD-card BOOT.BIN (DDR layout) or the included xsdb JTAG loader (OCM and DDR layouts; tools/scripts/zcu102 has the generic pattern). HW-tested on a ZCU102: DHCP + ping + UDP echo over both JTAG and SD boot.
VMK180 bring-up reusing ~90% of the ZCU102 port: A72 at EL3, GICv3, PL011 console, Cadence GEM0 + DP83867. Platform comes up from the PLM (boot PDI over JTAG); the GEM reference clock is left to the PLM (Versal CRL is PMC-protected). Poll-driven RX, all-address PHY scan preferring the linked PHY. HW-tested on a VMK180: DHCP + ping + UDP echo.
ZC702 bring-up: A9 in SVC mode, GIC-390, short-descriptor MMU, MPCore Global Timer (the A9 has no ARMv7 generic timer), UART1 console, Cadence GEM0 with a Marvell 88E1518 PHY driver (the ZC702 PHY, not DP83867), GEM clock/RGMII RX-clock via SLCR, poll-driven RX with the GEM IRQ masked, and non-cacheable OCM for DMA-coherent descriptors. FSBL-based xsdb JTAG loader. HW-tested on a ZC702: DHCP + ping + UDP echo.
dgarske
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| #ifndef ZCU102_UART_H | ||
| #define ZCU102_UART_H |
| void uart_putdec(uint32_t val); | ||
| void uart_putip4(ip4 ip); | ||
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| #endif /* ZCU102_UART_H */ |
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| #ifndef ZCU102_GIC_H | ||
| #define ZCU102_GIC_H |
| * dispatches, and EOIs the current interrupt. */ | ||
| void irq_dispatch(void); | ||
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| #endif /* ZCU102_GIC_H */ |
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| #ifndef ZCU102_GEM_H | ||
| #define ZCU102_GEM_H |
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| * TI DP83867IR PHY driver: 10/100/1000 RGMII PHY used on the ZCU102 | ||
| * dev board. We only need configuration (reset, RGMII TX/RX skew, | ||
| * auto-negotiation) and link status; no advanced features. |
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| * Workaround: on this ZynqMP / Cortex-A53 / GIC-400 combination, | ||
| * the GIC latches pending interrupts correctly but the CPU never | ||
| * takes the IRQ exception (root cause not pinned). Calling this | ||
| * function from the main loop is functionally equivalent. */ |
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| * Cadence GEM driver for Xilinx UltraScale+ MPSoC GEM3 (on-board RJ45 | ||
| * on ZCU102). Single-instance, RGMII, gigabit, polled TX, IRQ-driven | ||
| * RX. |
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| * Workaround: on this ZynqMP / Cortex-A53 / GIC-400 combination, | ||
| * the GIC latches pending interrupts correctly but the CPU never | ||
| * takes the IRQ exception (root cause not pinned). Calling this | ||
| * function from the main loop is functionally equivalent. */ |
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| * TI DP83867IR PHY driver: 10/100/1000 RGMII PHY used on the ZCU102 | ||
| * dev board. We only need configuration (reset, RGMII TX/RX skew, | ||
| * auto-negotiation) and link status; no advanced features. |
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Three bare-metal wolfIP ports (no Xilinx BSP, no RTOS), each demoing DHCP + ICMP ping + a UDP echo socket on port 7. All three are brought up on real hardware.
Ports
BOOT.BIN, DDR layout) or the included xsdb JTAG loader.Testing
Each port verified on its board: DHCP lease,
ping0% loss, andnc -u <ip> 7echo round-trip. ZCU102 verified over both JTAG load and SD-card boot.Notes
src/port/<plat>/).