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1. 4-bit-parity-protected-data-transmitter 4-bit-parity-protected-data-transmitter Public

   Verilog HDL implementation of a 4-bit even parity generator and parity checker with error detection, testbench simulation, and waveform verification.

   Verilog

2. 8-to-1-multiplexer-based-function-evaluator 8-to-1-multiplexer-based-function-evaluator Public

   Verilog implementation of an 8x1 Multiplexer using behavioral and gate-level modeling, including MUX-based realization of F(A,B,C) = Σm(1,2,4,7) with a self-checking testbench.

   Verilog