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hw: per-bank PLATFORM_MEMORY_OFFSET — fix U250 vx_busy hang at boot #342

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hw: per-bank PLATFORM_MEMORY_OFFSET — fix U250 vx_busy hang at boot #342

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16 changes: 14 additions & 2 deletions hw/rtl/afu/xrt/VX_afu_wrap.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -287,9 +287,21 @@ module VX_afu_wrap import VX_gpu_pkg::*; #(
wire [M_AXI_MEM_ADDR_WIDTH-1:0] m_axi_mem_awaddr_u [C_M_AXI_MEM_NUM_BANKS];
wire [M_AXI_MEM_ADDR_WIDTH-1:0] m_axi_mem_araddr_u [C_M_AXI_MEM_NUM_BANKS];

// Per-bank XRT BO base offsets. Each m_axi_mem_<i> port goes to a different
// xrt::bo (one per DDR/HBM channel) which XRT places at a different virtual
// base address, so a single global PLATFORM_MEMORY_OFFSET cannot cover all
// banks. PLATFORM_MEMORY_OFFSET_<i> overrides per bank; each defaults to
// PLATFORM_MEMORY_OFFSET so existing single-bank platforms (HBM, VCK5000)
// are unchanged.
wire [C_M_AXI_MEM_ADDR_WIDTH-1:0] platform_memory_offsets [4];
assign platform_memory_offsets[0] = C_M_AXI_MEM_ADDR_WIDTH'(`PLATFORM_MEMORY_OFFSET_0);
assign platform_memory_offsets[1] = C_M_AXI_MEM_ADDR_WIDTH'(`PLATFORM_MEMORY_OFFSET_1);
assign platform_memory_offsets[2] = C_M_AXI_MEM_ADDR_WIDTH'(`PLATFORM_MEMORY_OFFSET_2);
assign platform_memory_offsets[3] = C_M_AXI_MEM_ADDR_WIDTH'(`PLATFORM_MEMORY_OFFSET_3);

for (genvar i = 0; i < C_M_AXI_MEM_NUM_BANKS; ++i) begin : g_addressing
assign m_axi_mem_awaddr_a[i] = C_M_AXI_MEM_ADDR_WIDTH'(m_axi_mem_awaddr_u[i]) + C_M_AXI_MEM_ADDR_WIDTH'(`PLATFORM_MEMORY_OFFSET);
assign m_axi_mem_araddr_a[i] = C_M_AXI_MEM_ADDR_WIDTH'(m_axi_mem_araddr_u[i]) + C_M_AXI_MEM_ADDR_WIDTH'(`PLATFORM_MEMORY_OFFSET);
assign m_axi_mem_awaddr_a[i] = C_M_AXI_MEM_ADDR_WIDTH'(m_axi_mem_awaddr_u[i]) + platform_memory_offsets[i];
assign m_axi_mem_araddr_a[i] = C_M_AXI_MEM_ADDR_WIDTH'(m_axi_mem_araddr_u[i]) + platform_memory_offsets[i];
end

`SCOPE_IO_SWITCH (2);
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18 changes: 18 additions & 0 deletions hw/rtl/afu/xrt/vortex_afu.vh
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Expand Up @@ -18,6 +18,24 @@
`define PLATFORM_MEMORY_OFFSET 0
`endif

// Per-bank XRT BO base address. Each m_axi_mem_<i> port's outgoing AXI byte
// address gets this offset added so that Vortex's compile-time absolute
// addresses (STARTUP_ADDR, STACK_BASE_ADDR, ...) land inside the xrt::bo
// allocation that XRT placed in that bank. Defaults to PLATFORM_MEMORY_OFFSET
// (single offset for all banks) for back-compatibility.
`ifndef PLATFORM_MEMORY_OFFSET_0
`define PLATFORM_MEMORY_OFFSET_0 `PLATFORM_MEMORY_OFFSET
`endif
`ifndef PLATFORM_MEMORY_OFFSET_1
`define PLATFORM_MEMORY_OFFSET_1 `PLATFORM_MEMORY_OFFSET
`endif
`ifndef PLATFORM_MEMORY_OFFSET_2
`define PLATFORM_MEMORY_OFFSET_2 `PLATFORM_MEMORY_OFFSET
`endif
`ifndef PLATFORM_MEMORY_OFFSET_3
`define PLATFORM_MEMORY_OFFSET_3 `PLATFORM_MEMORY_OFFSET
`endif

`ifndef PLATFORM_MEMORY_ID_WIDTH
`define PLATFORM_MEMORY_ID_WIDTH 32
`endif
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8 changes: 6 additions & 2 deletions hw/syn/xilinx/xrt/platforms.mk
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Expand Up @@ -30,8 +30,12 @@ else ifneq ($(findstring xilinx_u280,$(XSA)),)
CONFIGS += -DPLATFORM_MEMORY_NUM_BANKS=32 -DPLATFORM_MEMORY_ADDR_WIDTH=33
VPP_FLAGS += --connectivity.sp vortex_afu_1.m_axi_mem_0:HBM[0:31]
else ifneq ($(findstring xilinx_u250,$(XSA)),)
# 64 GB of DDR4 with 4 channels (16 GB per channel)
CONFIGS += -DPLATFORM_MEMORY_NUM_BANKS=4 -DPLATFORM_MEMORY_ADDR_WIDTH=36
# 16 GB of DDR4 (single channel, bank 0). Multi-bank requires per-bank XRT
# VA offsets that aren't known at synthesis time without runtime plumbing;
# see follow-up PR for a DCR-based runtime path.
CONFIGS += -DPLATFORM_MEMORY_NUM_BANKS=1 -DPLATFORM_MEMORY_ADDR_WIDTH=34
VPP_FLAGS += --connectivity.sp vortex_afu_1.m_axi_mem_0:DDR[0]
CONFIGS += -DPLATFORM_MEMORY_OFFSET_0=40\'h4000000000
else ifneq ($(findstring xilinx_u200,$(XSA)),)
# 64 GB of DDR4 with 4 channels (16 GB per channel)
CONFIGS += -DPLATFORM_MEMORY_NUM_BANKS=4 -DPLATFORM_MEMORY_ADDR_WIDTH=36
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