Hands-on exercises for the Computer Architecture course at the University of Las Palmas de Gran Canaria (Spain) using Nios V-based soft SoCs and the DE0-Nano board
Lab 1. RISC-V instruction set architecture and programming of NiosV/m processor
Lab 3. Performance evaluation of pipelined processors
Lab 4. Nios V multiprocessor implementation, parallel programming, and performance evaluation
Lab 5. Nios V processor with customized architecture for a software application
- Terasic DE0-Nano board
- Desktop computer
- USB-A - miniUSB cable
- Windows 10
- Intel Quartus Prime Standard Edition Design Suite 23.1
- Intel Quartus Prime Standard Edition Design Suite 24.1
code: assembler and C programs
labs: pdf documents for hands-on exercises
SoC_configurations: binary files to configure the FPGA of a Terasic DE0-Nano board
2025 winter semester: 171 students enrolled, 7 student groups.
Lab hours: 30
2-hour sessions: 15
Lab-sesson/week: 1
Labs are based on principles presented in 30 one-hour lectures during the semester in parallel with the lab sessions. The main topics covered are: methodology for performance evaluation of RISC computers, microarchitecture of pipelined processors and its efficient programming, performance evaluation of cache memories, design and performance evaluation of main memory, static scheduling of instructions, out-of-order instruction execution, microarchitecture and evaluation of superscalar processors, VLIW architectures and microarchitectures, high-performance parallel computing using shared memory multi-core architectures, GPUs, multicomputers and application specific instruction set processors.
Practical experience on Computer Architecture using real FPGA-based hardware, assembly language programming using a RISC-based instruction set and several bare-metal computer systems, multi-thread programming, code optimization using information from the computer architecture, performance evaluation of processors and multiprocessors, performance evaluation of memory hierarchy including main memory and caches, programming, performance evaluation and customization of the microarchitecture of a general-purpose processor integrated into a System-on-Chip (SoC) or subsystem (SS).
Performance Architect (workload analysis, understand bottlenecks in cores and SoCs), CPU Core Microarchitecture/RTL Engineer (RTL design for sections of the processor pipeline, define the high-level architecture), Platform Hardware and Systems Engineer (development of hardware and systems), System and Solution Architect ((micro)architecture simulation, workloads characterization, C++/Python/Perl programming), GPU Platform Hardware Design Engineer (RTL coding, and simulation for graphics IPs), Platform Solutions Architect (translate requirements and key performance indicators into platform architecture encompassing hardware, software, SoCs, and other components designed to support a variety of systems, solutions, and applications), Platform Validation Engineer (develop verification plans for coherency/ memory/ power management/ security/ domains of pre-silicon SoC/SS), Security Research Engineer (design and implementation of scientific research projects for secure computing, cryptographic algorithms, communication, memory and networking), Silicon Architecture Engineer (logic & circuit design, physical design, validation and debug).
Another repository includes similar hands-on exercises using the Nios II soft processor that have been used in the training of more than 1,000 computer science undergraduate students for more than 10 years.
Benitez, D. (2024). Hands-on experience for undergraduate Computer Architecture courses using Nios V-based soft SoCs and real board. 2024 First Annual Soft RISC-V Systems Workshop. https://github.com/vipl-dbd/ComputerArchitecture_NiosV/blob/main/benitezSRvSnov24paper.pdf