Hands-on exercises for the Computer Architecture course at the University of Las Palmas de Gran Canaria (Spain) using Nios II-based System-on-Chips (SoCs) and the DE0-Nano board.
Lab 1. Nios II/e instruction set architecture and programming
Lab 3. Performance evaluation of pipelined processors
Lab 4. Nios II multiprocessor implementation, parallel programming, and performance evaluation
Lab 5. Nios II processor with customized architecture for a software application
- Terasic DE0-Nano board
- Desktop computer
- USB-A - miniUSB cable
- Windows 10
- Altera Quartus II Design Suite 13.1
- Altera Monitor Program 13.1
- Nios II Embedded Design Suite 13.1
./code: assembler and C programs
./labs: pdf documents for hands-on exercises
./SoC_configurations: binary files to configure the FPGA of a Terasic DE0-Nano board
The lab assignments described here have been used in the training of more than 1,000 computer science undergraduate students for more than 10 years.
2025 winter semester: 171 students enrolled, 7 student groups.
Week 1. Lab 1: summary, DE0-Nano board, Altera software tools, Nios II instruction set architecture, assembler programming, exercises. Hours: 2 (laboratory) + 2 (homework). Documents: guide, video (Spanish).
Week 2. Lab 1: subroutines, modification of a loaded instruction code, exercises: Fibonacci series, binary multiplication, dot product, binary division. Hours: 2 (laboratory) + 2 (homework). Documents: guide.
Week 3. Lab 1: test of developed assembly code projects on the DE0-Nano board. Hours: 2 (laboratory) + 2 (homework). Documents: guide.
Week 4. Lab 1: exam. Hours: 2 (laboratory) + 2 (homework).
Week 5. Lab 2: summary, memory hierarchy and its implementation on the DE0-Nano board, SDRAM memory device, SRAM on-chip memory, performance evaluation of Nios II/e soft core when SDRAM or SRAM are activated. Hours: 2 (laboratory) + 2 (homework). Documents: guide.
Week 6. Lab 2: cache memory size and block size of an unknown soft core microarchitecture are discovered (cache memory reverse engineering). Hours: 2 (laboratory) + 2 (homework). Documents: guide.
Week 7. Lab 2: cache memory size and block size of an unknown soft core microarchitecture are discovered (cache memory reverse engineering). Hours: 2 (laboratory) + 2 (homework). Documents: guide.
Week 8. Lab 2: exam. Hours: 2 (laboratory) + 2 (homework).
Week 9. Lab 3: counting executed instructions and calculating the average CPI (cycles per instruction). Hours: 2 (laboratory) + 2 (homework). Documents: guide.
Week 10. Lab 3: roofline curves for Nios II/e and Nios II/f processors. Hours: 2 (laboratory) + 2 (homework). Documents: guide.
Week 11. Lab 3: performance evaluation of instruction reordering. Hours: 2 (laboratory) + 2 (homework). Documents: guide.
Week 12. Lab 3: exam. Hours: 2 (laboratory) + 2 (homework).
Week 13. Lab 4: Two tutorials for programming a Nios II/e multiprocessor. Hours: 2 (laboratory) + 2 (homework). Documents: guide.
Week 14. Lab 4: Parallel programming of the matrix-vector algorithm and performance evaluation on two Nios II multiprocessors. Hours: 2 (laboratory) + 2 (homework). Documents: guide.
Week 15. Lab 4: Parallel programming of the matrix-matrix algorithm and performance evaluation on three Nios II multiprocessors. Hours: 2 (laboratory) + 2 (homework). Documents: guide.
Labs are based on principles presented in 30 one-hour lectures during the semester in parallel with the lab sessions. The main topics covered are: methodology for performance evaluation of RISC computers, microarchitecture of pipelined processors and its efficient programming, performance evaluation of cache memories, design and performance evaluation of main memory, static scheduling of instructions, out-of-order instruction execution, microarchitecture and evaluation of superscalar processors, VLIW architectures and microarchitectures, high-performance parallel computing using shared memory multi-core architectures, GPUs, multicomputers and application specific instruction set processors.
Practical experience on Computer Architecture using real FPGA-based hardware, assembly language programming using a RISC-based instruction set and several bare-metal computer systems, multi-thread programming, code optimization using information from the computer architecture, performance evaluation of processors and multiprocessors, performance evaluation of memory hierarchy including main memory and caches, programming, performance evaluation and customization of the microarchitecture of a general-purpose processor integrated into a System-on-Chip (SoC) or subsystem (SS).
Performance Architect (workload analysis, understand bottlenecks in cores and SoCs), CPU Core Microarchitecture/RTL Engineer (RTL design for sections of the processor pipeline, define the high-level architecture), Platform Hardware and Systems Engineer (development of hardware and systems), System and Solution Architect ((micro)architecture simulation, workloads characterization, C++/Python/Perl programming), GPU Platform Hardware Design Engineer (RTL coding, and simulation for graphics IPs), Platform Solutions Architect (translate requirements and key performance indicators into platform architecture encompassing hardware, software, SoCs, and other components designed to support a variety of systems, solutions, and applications), Platform Validation Engineer (develop verification plans for coherency/ memory/ power management/ security/ domains of pre-silicon SoC/SS), Security Research Engineer (design and implementation of scientific research projects for secure computing, cryptographic algorithms, communication, memory and networking), Silicon Architecture Engineer (logic & circuit design, physical design, validation and debug).
Another repository includes similar hands-on exercises using the Nios V soft processor.
Benitez, D. (2024). Hands-on experience for undergraduate Computer Architecture courses using Nios V-based soft SoCs and real board. 2024 First Annual Soft RISC-V Systems Workshop. https://github.com/vipl-dbd/ComputerArchitecture_NiosV/blob/main/benitezSRvSnov24paper.pdf