update vpr_tight_floorplan golden results

Author: zhaisitong

vtr_flow/tasks/regression_tests/vtr_reg_nightly_test5/vpr_tight_floorplan/config/golden_results.txt

@@ -1,4 +1,4 @@
 arch	circuit	script_params	vtr_flow_elapsed_time	vtr_max_mem_stage	vtr_max_mem	error	odin_synth_time	max_odin_mem	yosys_synth_time	max_yosys_mem	abc_depth	abc_synth_time	abc_cec_time	abc_sec_time	max_abc_mem	ace_time	max_ace_mem	num_clb	num_io	num_memories	num_mult	vpr_status	vpr_revision	vpr_build_info	vpr_compiler	vpr_compiled	hostname	rundir	max_vpr_mem	num_primary_inputs	num_primary_outputs	num_pre_packed_nets	num_pre_packed_blocks	num_netlist_clocks	num_post_packed_nets	num_post_packed_blocks	device_width	device_height	device_grid_tiles	device_limiting_resources	device_name	pack_mem	pack_time	placed_wirelength_est	place_mem	place_time	place_quench_time	placed_CPD_est	placed_setup_TNS_est	placed_setup_WNS_est	placed_geomean_nonvirtual_intradomain_critical_path_delay_est	place_delay_matrix_lookup_time	place_quench_timing_analysis_time	place_quench_sta_time	place_total_timing_analysis_time	place_total_sta_time	min_chan_width	routed_wirelength	min_chan_width_route_success_iteration	logic_block_area_total	logic_block_area_used	min_chan_width_routing_area_total	min_chan_width_routing_area_per_tile	min_chan_width_route_time	min_chan_width_total_timing_analysis_time	min_chan_width_total_sta_time	crit_path_routed_wirelength	crit_path_route_success_iteration	crit_path_total_nets_routed	crit_path_total_connections_routed	crit_path_total_heap_pushes	crit_path_total_heap_pops	critical_path_delay	geomean_nonvirtual_intradomain_critical_path_delay	setup_TNS	setup_WNS	hold_TNS	hold_WNS	crit_path_routing_area_total	crit_path_routing_area_per_tile	router_lookahead_computation_time	crit_path_route_time	crit_path_total_timing_analysis_time	crit_path_total_sta_time	
-stratixiv_arch_neuron.timing.xml	neuron_stratixiv_arch_timing.blif	common_-sdc_file_sdc/samples/neuron_stratixiv_arch_timing.sdc_-read_vpr_constraints_tasks/regression_tests/vtr_reg_nightly_test5/vpr_tight_floorplan/sixteenth.xml	0.37	vpr	856.00 KiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	exited with return code 127	unknown	unknown	unknown	unknown	virtual	/home/zhaisitong/worksapce/vtr2/vtr-verilog-to-routing/vtr_flow/tasks	856	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	
-stratixiv_arch_neuron.timing.xml	neuron_stratixiv_arch_timing.blif	common_-sdc_file_sdc/samples/neuron_stratixiv_arch_timing.sdc_-read_vpr_constraints_tasks/regression_tests/vtr_reg_nightly_test5/vpr_tight_floorplan/half_blocks_half.xml	0.35	vpr	932.00 KiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	exited with return code 127	unknown	unknown	unknown	unknown	virtual	/home/zhaisitong/worksapce/vtr2/vtr-verilog-to-routing/vtr_flow/tasks	932	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	
-stratixiv_arch_neuron.timing.xml	neuron_stratixiv_arch_timing.blif	common_-sdc_file_sdc/samples/neuron_stratixiv_arch_timing.sdc_-read_vpr_constraints_tasks/regression_tests/vtr_reg_nightly_test5/vpr_tight_floorplan/one_big_partition.xml	0.37	vpr	900.00 KiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	exited with return code 127	unknown	unknown	unknown	unknown	virtual	/home/zhaisitong/worksapce/vtr2/vtr-verilog-to-routing/vtr_flow/tasks	900	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	
+stratixiv_arch_neuron.timing.xml	neuron_stratixiv_arch_timing.blif	common_-sdc_file_sdc/samples/neuron_stratixiv_arch_timing.sdc_-read_vpr_constraints_tasks/regression_tests/vtr_reg_nightly_test5/vpr_tight_floorplan/sixteenth.xml	799.39	vpr	2.92 GiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	42	-1	-1	success	v8.0.0-6558-g07167c26e	release IPO VTR_ASSERT_LEVEL=2	GNU 11.2.0 on Linux-5.15.0-50-generic x86_64	2022-10-14T23:49:48	virtual	/home/zhaisitong/worksapce/vtr2/vtr-verilog-to-routing/vtr_flow/tasks	3062716	42	35	119888	86875	1	51809	3567	129	96	12384	-1	neuron	2030.2 MiB	224.15	597383	2910.1 MiB	152.46	0.81	7.61685	-74849.5	-6.61685	5.08623	58.44	0.262079	0.232955	50.6768	43.2043	-1	772505	48	0	0	2.28642e+08	18462.7	65.52	80.6627	70.338	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	
+stratixiv_arch_neuron.timing.xml	neuron_stratixiv_arch_timing.blif	common_-sdc_file_sdc/samples/neuron_stratixiv_arch_timing.sdc_-read_vpr_constraints_tasks/regression_tests/vtr_reg_nightly_test5/vpr_tight_floorplan/half_blocks_half.xml	674.41	vpr	2.73 GiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	42	-1	-1	success	v8.0.0-6558-g07167c26e	release IPO VTR_ASSERT_LEVEL=2	GNU 11.2.0 on Linux-5.15.0-50-generic x86_64	2022-10-14T23:49:48	virtual	/home/zhaisitong/worksapce/vtr2/vtr-verilog-to-routing/vtr_flow/tasks	2864032	42	35	119888	86875	1	51282	3422	129	96	12384	-1	neuron	1830.1 MiB	112.49	596408	2717.5 MiB	158.00	0.72	8.25008	-74642.4	-7.25008	5.56231	59.35	0.274684	0.232207	53.3837	45.3298	-1	773463	30	0	0	2.28642e+08	18462.7	52.31	73.4046	63.5131	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	
+stratixiv_arch_neuron.timing.xml	neuron_stratixiv_arch_timing.blif	common_-sdc_file_sdc/samples/neuron_stratixiv_arch_timing.sdc_-read_vpr_constraints_tasks/regression_tests/vtr_reg_nightly_test5/vpr_tight_floorplan/one_big_partition.xml	651.65	vpr	2.73 GiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	42	-1	-1	success	v8.0.0-6558-g07167c26e	release IPO VTR_ASSERT_LEVEL=2	GNU 11.2.0 on Linux-5.15.0-50-generic x86_64	2022-10-14T23:49:48	virtual	/home/zhaisitong/worksapce/vtr2/vtr-verilog-to-routing/vtr_flow/tasks	2866000	42	35	119888	86875	1	51283	3425	129	96	12384	-1	neuron	1832.1 MiB	115.72	596968	2719.5 MiB	121.72	0.80	8.38198	-70951.7	-7.38198	5.24439	61.07	0.276509	0.233816	40.1409	34.0809	-1	770923	29	0	0	2.28642e+08	18462.7	54.69	59.6691	51.82	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1