change 'strong_tight_floorplan' to 'vpr_tight_floorplan'

Author: zhaisitong

vtr_flow/tasks/regression_tests/vtr_reg_nightly_test5/strong_tight_floorplan/config/golden_results.txt

@@ -1,2 +1,2 @@
 regression_tests/vtr_reg_nightly_test5/vpr_ispd
-regression_tests/vtr_reg_nightly_test5/strong_tight_floorplan
+regression_tests/vtr_reg_nightly_test5/vpr_tight_floorplan

vtr_flow/tasks/regression_tests/vtr_reg_nightly_test5/task_list.txt

@@ -3,10 +3,10 @@
 ##############################################
 
 # Path to directory of circuits to use
-circuits_dir=tasks/regression_tests/vtr_reg_nightly_test5/strong_tight_floorplan
+circuits_dir=tasks/regression_tests/vtr_reg_nightly_test5/vpr_tight_floorplan
 
 # Path to directory of architectures to use
-archs_dir=tasks/regression_tests/vtr_reg_nightly_test5/strong_tight_floorplan
+archs_dir=tasks/regression_tests/vtr_reg_nightly_test5/vpr_tight_floorplan
 
 # Add circuits to list to sweep
 circuit_list_add=neuron_stratixiv_arch_timing.blif
@@ -25,6 +25,6 @@ pass_requirements_file=pass_requirements.txt
 
 # Script parameters
 script_params_common =-starting_stage vpr --route_chan_width 300 --max_router_iterations 400 --router_lookahead map --initial_pres_fac 1.0 --router_profiler_astar_fac 1.5 --seed 3 --device neuron 
-script_params_list_add = -sdc_file sdc/samples/neuron_stratixiv_arch_timing.sdc -read_vpr_constraints tasks/regression_tests/vtr_reg_nightly_test5/strong_tight_floorplan/sixteenth.xml
-script_params_list_add = -sdc_file sdc/samples/neuron_stratixiv_arch_timing.sdc -read_vpr_constraints tasks/regression_tests/vtr_reg_nightly_test5/strong_tight_floorplan/half_blocks_half.xml
-script_params_list_add = -sdc_file sdc/samples/neuron_stratixiv_arch_timing.sdc -read_vpr_constraints tasks/regression_tests/vtr_reg_nightly_test5/strong_tight_floorplan/one_big_partition.xml
+script_params_list_add = -sdc_file sdc/samples/neuron_stratixiv_arch_timing.sdc -read_vpr_constraints tasks/regression_tests/vtr_reg_nightly_test5/vpr_tight_floorplan/sixteenth.xml
+script_params_list_add = -sdc_file sdc/samples/neuron_stratixiv_arch_timing.sdc -read_vpr_constraints tasks/regression_tests/vtr_reg_nightly_test5/vpr_tight_floorplan/half_blocks_half.xml
+script_params_list_add = -sdc_file sdc/samples/neuron_stratixiv_arch_timing.sdc -read_vpr_constraints tasks/regression_tests/vtr_reg_nightly_test5/vpr_tight_floorplan/one_big_partition.xml

…strong_tight_floorplan/config/config.txt …t5/vpr_tight_floorplan/config/config.txtvtr_flow/tasks/regression_tests/vtr_reg_nightly_test5/strong_tight_floorplan/config/config.txt renamed to vtr_flow/tasks/regression_tests/vtr_reg_nightly_test5/vpr_tight_floorplan/config/config.txt vtr_flow/tasks/regression_tests/vtr_reg_nightly_test5/strong_tight_floorplan/config/config.txt renamed to vtr_flow/tasks/regression_tests/vtr_reg_nightly_test5/vpr_tight_floorplan/config/config.txt

@@ -0,0 +1,4 @@
+arch	circuit	script_params	vtr_flow_elapsed_time	vtr_max_mem_stage	vtr_max_mem	error	odin_synth_time	max_odin_mem	yosys_synth_time	max_yosys_mem	abc_depth	abc_synth_time	abc_cec_time	abc_sec_time	max_abc_mem	ace_time	max_ace_mem	num_clb	num_io	num_memories	num_mult	vpr_status	vpr_revision	vpr_build_info	vpr_compiler	vpr_compiled	hostname	rundir	max_vpr_mem	num_primary_inputs	num_primary_outputs	num_pre_packed_nets	num_pre_packed_blocks	num_netlist_clocks	num_post_packed_nets	num_post_packed_blocks	device_width	device_height	device_grid_tiles	device_limiting_resources	device_name	pack_mem	pack_time	placed_wirelength_est	place_mem	place_time	place_quench_time	placed_CPD_est	placed_setup_TNS_est	placed_setup_WNS_est	placed_geomean_nonvirtual_intradomain_critical_path_delay_est	place_delay_matrix_lookup_time	place_quench_timing_analysis_time	place_quench_sta_time	place_total_timing_analysis_time	place_total_sta_time	min_chan_width	routed_wirelength	min_chan_width_route_success_iteration	logic_block_area_total	logic_block_area_used	min_chan_width_routing_area_total	min_chan_width_routing_area_per_tile	min_chan_width_route_time	min_chan_width_total_timing_analysis_time	min_chan_width_total_sta_time	crit_path_routed_wirelength	crit_path_route_success_iteration	crit_path_total_nets_routed	crit_path_total_connections_routed	crit_path_total_heap_pushes	crit_path_total_heap_pops	critical_path_delay	geomean_nonvirtual_intradomain_critical_path_delay	setup_TNS	setup_WNS	hold_TNS	hold_WNS	crit_path_routing_area_total	crit_path_routing_area_per_tile	router_lookahead_computation_time	crit_path_route_time	crit_path_total_timing_analysis_time	crit_path_total_sta_time	
+stratixiv_arch_neuron.timing.xml	neuron_stratixiv_arch_timing.blif	common_-sdc_file_sdc/samples/neuron_stratixiv_arch_timing.sdc_-read_vpr_constraints_tasks/regression_tests/vtr_reg_nightly_test5/vpr_tight_floorplan/sixteenth.xml	0.37	vpr	856.00 KiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	exited with return code 127	unknown	unknown	unknown	unknown	virtual	/home/zhaisitong/worksapce/vtr2/vtr-verilog-to-routing/vtr_flow/tasks	856	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	
+stratixiv_arch_neuron.timing.xml	neuron_stratixiv_arch_timing.blif	common_-sdc_file_sdc/samples/neuron_stratixiv_arch_timing.sdc_-read_vpr_constraints_tasks/regression_tests/vtr_reg_nightly_test5/vpr_tight_floorplan/half_blocks_half.xml	0.35	vpr	932.00 KiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	exited with return code 127	unknown	unknown	unknown	unknown	virtual	/home/zhaisitong/worksapce/vtr2/vtr-verilog-to-routing/vtr_flow/tasks	932	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	
+stratixiv_arch_neuron.timing.xml	neuron_stratixiv_arch_timing.blif	common_-sdc_file_sdc/samples/neuron_stratixiv_arch_timing.sdc_-read_vpr_constraints_tasks/regression_tests/vtr_reg_nightly_test5/vpr_tight_floorplan/one_big_partition.xml	0.37	vpr	900.00 KiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	exited with return code 127	unknown	unknown	unknown	unknown	virtual	/home/zhaisitong/worksapce/vtr2/vtr-verilog-to-routing/vtr_flow/tasks	900	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1