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vaughnbetzvaughnbetz
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Merge pull request #2084 from verilog-to-routing/pack_malloc_to_new
Pack malloc to new
2 parents 2577b52 + 5f46eb7 commit 7989197

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17 files changed

+332
-268
lines changed

17 files changed

+332
-268
lines changed

‎libs/libarchfpga/src/arch_util.cpp‎

Lines changed: 22 additions & 54 deletions
Original file line numberDiff line numberDiff line change
@@ -298,7 +298,7 @@ static void free_all_pb_graph_nodes(std::vector<t_logical_block_type>& type_desc
298298
if (type.pb_type) {
299299
if (type.pb_graph_head) {
300300
free_pb_graph(type.pb_graph_head);
301-
vtr::free(type.pb_graph_head);
301+
delete type.pb_graph_head;
302302
}
303303
}
304304
}
@@ -316,78 +316,46 @@ static void free_pb_graph(t_pb_graph_node* pb_graph_node) {
316316
/* Free ports for pb graph node */
317317
for (i = 0; i < pb_graph_node->num_input_ports; i++) {
318318
for (j = 0; j < pb_graph_node->num_input_pins[i]; j++) {
319-
if (pb_graph_node->input_pins[i][j].pin_timing)
320-
vtr::free(pb_graph_node->input_pins[i][j].pin_timing);
321-
if (pb_graph_node->input_pins[i][j].pin_timing_del_max)
322-
vtr::free(pb_graph_node->input_pins[i][j].pin_timing_del_max);
323-
if (pb_graph_node->input_pins[i][j].pin_timing_del_min)
324-
vtr::free(pb_graph_node->input_pins[i][j].pin_timing_del_min);
325-
if (pb_graph_node->input_pins[i][j].input_edges)
326-
vtr::free(pb_graph_node->input_pins[i][j].input_edges);
327-
if (pb_graph_node->input_pins[i][j].output_edges)
328-
vtr::free(pb_graph_node->input_pins[i][j].output_edges);
329319
if (pb_graph_node->input_pins[i][j].parent_pin_class)
330-
vtr::free(pb_graph_node->input_pins[i][j].parent_pin_class);
320+
delete[] pb_graph_node->input_pins[i][j].parent_pin_class;
331321
}
332322
delete[] pb_graph_node->input_pins[i];
333323
}
334324
for (i = 0; i < pb_graph_node->num_output_ports; i++) {
335325
for (j = 0; j < pb_graph_node->num_output_pins[i]; j++) {
336-
if (pb_graph_node->output_pins[i][j].pin_timing)
337-
vtr::free(pb_graph_node->output_pins[i][j].pin_timing);
338-
if (pb_graph_node->output_pins[i][j].pin_timing_del_max)
339-
vtr::free(pb_graph_node->output_pins[i][j].pin_timing_del_max);
340-
if (pb_graph_node->output_pins[i][j].pin_timing_del_min)
341-
vtr::free(pb_graph_node->output_pins[i][j].pin_timing_del_min);
342-
if (pb_graph_node->output_pins[i][j].input_edges)
343-
vtr::free(pb_graph_node->output_pins[i][j].input_edges);
344-
if (pb_graph_node->output_pins[i][j].output_edges)
345-
vtr::free(pb_graph_node->output_pins[i][j].output_edges);
346326
if (pb_graph_node->output_pins[i][j].parent_pin_class)
347-
vtr::free(pb_graph_node->output_pins[i][j].parent_pin_class);
327+
delete[] pb_graph_node->output_pins[i][j].parent_pin_class;
348328

349329
if (pb_graph_node->output_pins[i][j].list_of_connectable_input_pin_ptrs) {
350330
for (k = 0; k < pb_graph_node->pb_type->depth; k++) {
351-
if (pb_graph_node->output_pins[i][j].list_of_connectable_input_pin_ptrs[k]) {
352-
vtr::free(pb_graph_node->output_pins[i][j].list_of_connectable_input_pin_ptrs[k]);
353-
}
331+
delete[] pb_graph_node->output_pins[i][j].list_of_connectable_input_pin_ptrs[k];
354332
}
355-
vtr::free(pb_graph_node->output_pins[i][j].list_of_connectable_input_pin_ptrs);
333+
delete[] pb_graph_node->output_pins[i][j].list_of_connectable_input_pin_ptrs;
356334
}
357335

358336
if (pb_graph_node->output_pins[i][j].num_connectable_primitive_input_pins)
359-
vtr::free(pb_graph_node->output_pins[i][j].num_connectable_primitive_input_pins);
337+
delete[] pb_graph_node->output_pins[i][j].num_connectable_primitive_input_pins;
360338
}
361339
delete[] pb_graph_node->output_pins[i];
362340
}
363341
for (i = 0; i < pb_graph_node->num_clock_ports; i++) {
364342
for (j = 0; j < pb_graph_node->num_clock_pins[i]; j++) {
365-
if (pb_graph_node->clock_pins[i][j].pin_timing)
366-
vtr::free(pb_graph_node->clock_pins[i][j].pin_timing);
367-
if (pb_graph_node->clock_pins[i][j].pin_timing_del_max)
368-
vtr::free(pb_graph_node->clock_pins[i][j].pin_timing_del_max);
369-
if (pb_graph_node->clock_pins[i][j].pin_timing_del_min)
370-
vtr::free(pb_graph_node->clock_pins[i][j].pin_timing_del_min);
371-
if (pb_graph_node->clock_pins[i][j].input_edges)
372-
vtr::free(pb_graph_node->clock_pins[i][j].input_edges);
373-
if (pb_graph_node->clock_pins[i][j].output_edges)
374-
vtr::free(pb_graph_node->clock_pins[i][j].output_edges);
375343
if (pb_graph_node->clock_pins[i][j].parent_pin_class)
376-
vtr::free(pb_graph_node->clock_pins[i][j].parent_pin_class);
344+
delete[] pb_graph_node->clock_pins[i][j].parent_pin_class;
377345
}
378346
delete[] pb_graph_node->clock_pins[i];
379347
}
380348

381-
vtr::free(pb_graph_node->input_pins);
382-
vtr::free(pb_graph_node->output_pins);
383-
vtr::free(pb_graph_node->clock_pins);
349+
delete[] pb_graph_node->input_pins;
350+
delete[] pb_graph_node->output_pins;
351+
delete[] pb_graph_node->clock_pins;
384352

385-
vtr::free(pb_graph_node->num_input_pins);
386-
vtr::free(pb_graph_node->num_output_pins);
387-
vtr::free(pb_graph_node->num_clock_pins);
353+
delete[] pb_graph_node->num_input_pins;
354+
delete[] pb_graph_node->num_output_pins;
355+
delete[] pb_graph_node->num_clock_pins;
388356

389-
vtr::free(pb_graph_node->input_pin_class_size);
390-
vtr::free(pb_graph_node->output_pin_class_size);
357+
delete[] pb_graph_node->input_pin_class_size;
358+
delete[] pb_graph_node->output_pin_class_size;
391359

392360
if (pb_graph_node->interconnect_pins) {
393361
for (i = 0; i < pb_graph_node->pb_type->num_modes; i++) {
@@ -403,19 +371,19 @@ static void free_pb_graph(t_pb_graph_node* pb_graph_node) {
403371

404372
t_interconnect_power* interconn_power = interconn->interconnect_power;
405373
for (int iport = 0; iport < interconn_power->num_input_ports; ++iport) {
406-
vtr::free(pb_graph_node->interconnect_pins[i][j].input_pins[iport]);
374+
delete[] pb_graph_node->interconnect_pins[i][j].input_pins[iport];
407375
}
408376
for (int iport = 0; iport < interconn_power->num_output_ports; ++iport) {
409-
vtr::free(pb_graph_node->interconnect_pins[i][j].output_pins[iport]);
377+
delete[] pb_graph_node->interconnect_pins[i][j].output_pins[iport];
410378
}
411-
vtr::free(pb_graph_node->interconnect_pins[i][j].input_pins);
412-
vtr::free(pb_graph_node->interconnect_pins[i][j].output_pins);
379+
delete[] pb_graph_node->interconnect_pins[i][j].input_pins;
380+
delete[] pb_graph_node->interconnect_pins[i][j].output_pins;
413381
}
414-
vtr::free(pb_graph_node->interconnect_pins[i]);
382+
delete[] pb_graph_node->interconnect_pins[i];
415383
}
416384
}
417-
vtr::free(pb_graph_node->interconnect_pins);
418-
vtr::free(pb_graph_node->pb_node_power);
385+
delete[] pb_graph_node->interconnect_pins;
386+
delete pb_graph_node->pb_node_power;
419387

420388
for (i = 0; i < pb_type->num_modes; i++) {
421389
for (j = 0; j < pb_type->modes[i].num_pb_type_children; j++) {

‎libs/libarchfpga/src/physical_types.h‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1235,9 +1235,9 @@ class t_pb_graph_pin {
12351235
public:
12361236
t_port* port = nullptr;
12371237
int pin_number = 0;
1238-
t_pb_graph_edge** input_edges = nullptr; /* [0..num_input_edges] */
1238+
std::vector<t_pb_graph_edge*> input_edges; /* [0..num_input_edges] */
12391239
int num_input_edges = 0;
1240-
t_pb_graph_edge** output_edges = nullptr; /* [0..num_output_edges] */
1240+
std::vector<t_pb_graph_edge*> output_edges; /* [0..num_output_edges] */
12411241
int num_output_edges = 0;
12421242

12431243
t_pb_graph_node* parent_node = nullptr;
@@ -1256,9 +1256,9 @@ class t_pb_graph_pin {
12561256

12571257
/* combinational timing information */
12581258
int num_pin_timing = 0; /* Number of ipin to opin timing edges*/
1259-
t_pb_graph_pin** pin_timing = nullptr; /* timing edge sink pins [0..num_pin_timing-1]*/
1260-
float* pin_timing_del_max = nullptr; /* primitive ipin to opin max-delay [0..num_pin_timing-1]*/
1261-
float* pin_timing_del_min = nullptr; /* primitive ipin to opin min-delay [0..num_pin_timing-1]*/
1259+
std::vector<t_pb_graph_pin*> pin_timing; /* timing edge sink pins [0..num_pin_timing-1]*/
1260+
std::vector<float> pin_timing_del_max; /* primitive ipin to opin max-delay [0..num_pin_timing-1]*/
1261+
std::vector<float> pin_timing_del_min; /* primitive ipin to opin min-delay [0..num_pin_timing-1]*/
12621262
int num_pin_timing_del_max_annotated = 0; //The list of valid pin_timing_del_max entries runs from [0..num_pin_timing_del_max_annotated-1]
12631263
int num_pin_timing_del_min_annotated = 0; //The list of valid pin_timing_del_max entries runs from [0..num_pin_timing_del_min_annotated-1]
12641264

@@ -1333,7 +1333,7 @@ class t_pb_graph_edge {
13331333

13341334
/* pack pattern info */
13351335
int num_pack_patterns;
1336-
const char** pack_pattern_names;
1336+
std::vector<const char*> pack_pattern_names;
13371337
int* pack_pattern_indices;
13381338
bool infer_pattern;
13391339

‎libs/libvtrutil/src/vtr_memory.cpp‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -6,6 +6,7 @@
66
#include "vtr_memory.h"
77
#include "vtr_error.h"
88
#include "vtr_util.h"
9+
#include "vtr_log.h"
910

1011
#ifndef __GLIBC__
1112
# include <stdlib.h>

‎vpr/src/base/read_netlist.cpp‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -751,10 +751,10 @@ static void processPorts(pugi::xml_node Parent, t_pb* pb, t_pb_routes& pb_route,
751751
}
752752
}
753753
for (j = 0; j < num_sets; j++) {
754-
free(pin_node[j]);
754+
delete[] pin_node[j];
755755
}
756-
free(pin_node);
757-
free(num_ptrs);
756+
delete[] pin_node;
757+
delete[] num_ptrs;
758758
if (!found) {
759759
vpr_throw(VPR_ERROR_NET_F, netlist_file_name, loc_data.line(Cur),
760760
"Unknown interconnect %s connecting to pin %s.\n",
@@ -820,10 +820,10 @@ static void processPorts(pugi::xml_node Parent, t_pb* pb, t_pb_routes& pb_route,
820820
}
821821
}
822822
for (j = 0; j < num_sets; j++) {
823-
free(pin_node[j]);
823+
delete[] pin_node[j];
824824
}
825-
free(pin_node);
826-
free(num_ptrs);
825+
delete[] pin_node;
826+
delete[] num_ptrs;
827827
if (!found) {
828828
vpr_throw(VPR_ERROR_NET_F, netlist_file_name, loc_data.line(Cur),
829829
"Unknown interconnect %s connecting to pin %s.\n",

‎vpr/src/base/vpr_context.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -323,7 +323,7 @@ struct ClusteringHelperContext : public Context {
323323
t_ext_pin_util_targets target_external_pin_util;
324324

325325
~ClusteringHelperContext() {
326-
free(primitives_list);
326+
delete[] primitives_list;
327327
}
328328
};
329329

‎vpr/src/base/vpr_types.cpp‎

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -236,31 +236,31 @@ void free_cluster_placement_stats(t_cluster_placement_stats* cluster_placement_s
236236
cur = cluster_placement_stats_list[index].tried;
237237
while (cur != nullptr) {
238238
next = cur->next_primitive;
239-
free(cur);
239+
delete cur;
240240
cur = next;
241241
}
242242
cur = cluster_placement_stats_list[index].in_flight;
243243
while (cur != nullptr) {
244244
next = cur->next_primitive;
245-
free(cur);
245+
delete cur;
246246
cur = next;
247247
}
248248
cur = cluster_placement_stats_list[index].invalid;
249249
while (cur != nullptr) {
250250
next = cur->next_primitive;
251-
free(cur);
251+
delete cur;
252252
cur = next;
253253
}
254254
for (int j = 0; j < cluster_placement_stats_list[index].num_pb_types; j++) {
255255
cur = cluster_placement_stats_list[index].valid_primitives[j]->next_primitive;
256256
while (cur != nullptr) {
257257
next = cur->next_primitive;
258-
free(cur);
258+
delete cur;
259259
cur = next;
260260
}
261-
free(cluster_placement_stats_list[index].valid_primitives[j]);
261+
delete cluster_placement_stats_list[index].valid_primitives[j];
262262
}
263-
free(cluster_placement_stats_list[index].valid_primitives);
263+
delete[] cluster_placement_stats_list[index].valid_primitives;
264264
}
265-
free(cluster_placement_stats_list);
265+
delete[] cluster_placement_stats_list;
266266
}

‎vpr/src/pack/cluster.cpp‎

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -189,8 +189,9 @@ std::map<t_logical_block_type_ptr, size_t> do_clustering(const t_packer_opts& pa
189189
get_max_cluster_size_and_pb_depth(helper_ctx.max_cluster_size, max_pb_depth);
190190

191191
if (packer_opts.hill_climbing_flag) {
192-
clustering_data.hill_climbing_inputs_avail = (int*)vtr::calloc(helper_ctx.max_cluster_size + 1,
193-
sizeof(int));
192+
clustering_data.hill_climbing_inputs_avail = new int[helper_ctx.max_cluster_size + 1];
193+
for (int i = 0; i < helper_ctx.max_cluster_size + 1; i++)
194+
clustering_data.hill_climbing_inputs_avail[i] = 0;
194195
} else {
195196
clustering_data.hill_climbing_inputs_avail = nullptr; /* if used, die hard */
196197
}

‎vpr/src/pack/cluster_feasibility_filter.cpp‎

Lines changed: 32 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -27,6 +27,7 @@
2727
* Date: May 16, 2012
2828
*/
2929

30+
#include <vector>
3031
#include "vtr_assert.h"
3132
#include "vtr_log.h"
3233
#include "vtr_memory.h"
@@ -95,25 +96,27 @@ static void alloc_pin_classes_in_pb_graph_node(t_pb_graph_node* pb_graph_node) {
9596
/* allocate space */
9697
for (i = 0; i < pb_graph_node->num_input_ports; i++) {
9798
for (j = 0; j < pb_graph_node->num_input_pins[i]; j++) {
98-
pb_graph_node->input_pins[i][j].parent_pin_class = (int*)vtr::calloc(pb_graph_node->pb_type->depth, sizeof(int));
99+
pb_graph_node->input_pins[i][j].parent_pin_class = new int[pb_graph_node->pb_type->depth];
99100
for (k = 0; k < pb_graph_node->pb_type->depth; k++) {
100101
pb_graph_node->input_pins[i][j].parent_pin_class[k] = OPEN;
101102
}
102103
}
103104
}
104105
for (i = 0; i < pb_graph_node->num_output_ports; i++) {
105106
for (j = 0; j < pb_graph_node->num_output_pins[i]; j++) {
106-
pb_graph_node->output_pins[i][j].parent_pin_class = (int*)vtr::calloc(pb_graph_node->pb_type->depth, sizeof(int));
107-
pb_graph_node->output_pins[i][j].list_of_connectable_input_pin_ptrs = (t_pb_graph_pin***)vtr::calloc(pb_graph_node->pb_type->depth, sizeof(t_pb_graph_pin**));
108-
pb_graph_node->output_pins[i][j].num_connectable_primitive_input_pins = (int*)vtr::calloc(pb_graph_node->pb_type->depth, sizeof(int));
107+
pb_graph_node->output_pins[i][j].parent_pin_class = new int[pb_graph_node->pb_type->depth];
108+
pb_graph_node->output_pins[i][j].list_of_connectable_input_pin_ptrs = new t_pb_graph_pin**[pb_graph_node->pb_type->depth];
109+
pb_graph_node->output_pins[i][j].num_connectable_primitive_input_pins = new int[pb_graph_node->pb_type->depth];
109110
for (k = 0; k < pb_graph_node->pb_type->depth; k++) {
111+
pb_graph_node->output_pins[i][j].list_of_connectable_input_pin_ptrs[k] = nullptr;
112+
pb_graph_node->output_pins[i][j].num_connectable_primitive_input_pins[k] = 0;
110113
pb_graph_node->output_pins[i][j].parent_pin_class[k] = OPEN;
111114
}
112115
}
113116
}
114117
for (i = 0; i < pb_graph_node->num_clock_ports; i++) {
115118
for (j = 0; j < pb_graph_node->num_clock_pins[i]; j++) {
116-
pb_graph_node->clock_pins[i][j].parent_pin_class = (int*)vtr::calloc(pb_graph_node->pb_type->depth, sizeof(int));
119+
pb_graph_node->clock_pins[i][j].parent_pin_class = new int[pb_graph_node->pb_type->depth];
117120
for (k = 0; k < pb_graph_node->pb_type->depth; k++) {
118121
pb_graph_node->clock_pins[i][j].parent_pin_class[k] = OPEN;
119122
}
@@ -261,9 +264,13 @@ static void load_pin_class_by_depth(t_pb_graph_node* pb_graph_node,
261264
if (pb_graph_node->pb_type->depth == depth && !pb_graph_node->is_primitive()) {
262265
/* Record pin class information for cluster */
263266
pb_graph_node->num_input_pin_class = *input_count + 1; /* number of input pin classes discovered + 1 for primitive inputs not reachable from cluster input pins */
264-
pb_graph_node->input_pin_class_size = (int*)vtr::calloc(*input_count + 1, sizeof(int));
267+
pb_graph_node->input_pin_class_size = new int[*input_count + 1];
268+
for (i = 0; i < *input_count + 1; i++) /* zero-initializing */
269+
pb_graph_node->input_pin_class_size[i] = 0;
265270
pb_graph_node->num_output_pin_class = *output_count + 1; /* number of output pin classes discovered + 1 for primitive inputs not reachable from cluster input pins */
266-
pb_graph_node->output_pin_class_size = (int*)vtr::calloc(*output_count + 1, sizeof(int));
271+
pb_graph_node->output_pin_class_size = new int[*output_count + 1];
272+
for (i = 0; i < *output_count + 1; i++) /* zero-initializing */
273+
pb_graph_node->output_pin_class_size[i] = 0;
267274
sum_pin_class(pb_graph_node);
268275
}
269276
}
@@ -315,10 +322,24 @@ static void expand_pb_graph_node_and_load_output_to_input_connections(t_pb_graph
315322
if (current_pb_graph_pin->is_primitive_pin()
316323
&& current_pb_graph_pin->port->type == IN_PORT) {
317324
reference_pin->num_connectable_primitive_input_pins[depth]++;
318-
reference_pin->list_of_connectable_input_pin_ptrs[depth] = (t_pb_graph_pin**)vtr::realloc(
319-
reference_pin->list_of_connectable_input_pin_ptrs[depth],
320-
reference_pin->num_connectable_primitive_input_pins[depth]
321-
* sizeof(t_pb_graph_pin*));
325+
326+
if (reference_pin->num_connectable_primitive_input_pins[depth] - 1 > 0) {
327+
std::vector<t_pb_graph_pin*> temp(reference_pin->list_of_connectable_input_pin_ptrs[depth],
328+
reference_pin->list_of_connectable_input_pin_ptrs[depth] + reference_pin->num_connectable_primitive_input_pins[depth] - 1);
329+
330+
delete[] reference_pin->list_of_connectable_input_pin_ptrs[depth];
331+
reference_pin->list_of_connectable_input_pin_ptrs[depth] = new t_pb_graph_pin*[reference_pin->num_connectable_primitive_input_pins[depth]];
332+
for (i = 0; i < reference_pin->num_connectable_primitive_input_pins[depth] - 1; i++)
333+
reference_pin->list_of_connectable_input_pin_ptrs[depth][i] = temp[i];
334+
335+
reference_pin->list_of_connectable_input_pin_ptrs[depth][reference_pin->num_connectable_primitive_input_pins[depth]
336+
- 1]
337+
= current_pb_graph_pin;
338+
}
339+
340+
else {
341+
reference_pin->list_of_connectable_input_pin_ptrs[depth] = new t_pb_graph_pin*[reference_pin->num_connectable_primitive_input_pins[depth]];
342+
}
322343
reference_pin->list_of_connectable_input_pin_ptrs[depth][reference_pin->num_connectable_primitive_input_pins[depth]
323344
- 1]
324345
= current_pb_graph_pin;

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