Merge branch 'master' into pack_malloc_to_new

Author: jmah76

.github/workflows/test.yml

@@ -155,17 +155,17 @@ jobs:
         include: [
           {
             name: 'Basic',
-            params: '-DVTR_ASSERT_LEVEL=3 -DWITH_BLIFEXPLORER=on',
+            params: '-DVTR_ASSERT_LEVEL=3 -DWITH_BLIFEXPLORER=on -DODIN_USE_YOSYS=ON',
             suite: 'vtr_reg_basic'
           },
           {
             name: 'Basic with NO_GRAPHICS',
-            params: '-DVTR_ASSERT_LEVEL=3 -DWITH_BLIFEXPLORER=on -DVPR_USE_EZGL=off',
+            params: '-DVTR_ASSERT_LEVEL=3 -DWITH_BLIFEXPLORER=on -DVPR_USE_EZGL=off -DODIN_USE_YOSYS=ON',
             suite: 'vtr_reg_basic'
           },
           {
             name: 'Basic with VTR_ENABLE_DEBUG_LOGGING',
-            params: '-DVTR_ASSERT_LEVEL=3 -DWITH_BLIFEXPLORER=on -DVTR_ENABLE_DEBUG_LOGGING=on',
+            params: '-DVTR_ASSERT_LEVEL=3 -DWITH_BLIFEXPLORER=on -DVTR_ENABLE_DEBUG_LOGGING=on -DODIN_USE_YOSYS=ON',
             suite: 'vtr_reg_basic'
           },
           {
@@ -238,7 +238,7 @@ jobs:
 
     - name: Test
       env:
-        CMAKE_PARAMS: '-DVTR_ASSERT_LEVEL=3 -DVTR_ENABLE_SANITIZE=on -DVTR_IPO_BUILD=off -DWITH_BLIFEXPLORER=on'
+        CMAKE_PARAMS: '-DVTR_ASSERT_LEVEL=3 -DVTR_ENABLE_SANITIZE=on -DVTR_IPO_BUILD=off -DWITH_BLIFEXPLORER=on -DODIN_USE_YOSYS=ON'
         BUILD_TYPE: debug
         LSAN_OPTIONS: 'exitcode=42' #Use a non-standard exit code to ensure LSAN errors are detected
       run: |

.gitignore

@@ -100,6 +100,11 @@ ODIN_II/usefull_tools/**/track_completed
 *.o
 *.a
 
+#
+#Yosys exec dir
+#
+Yosys
+
 #
 #Python
 #

ODIN_II/SRC/BLIFReader.cpp

@@ -336,10 +336,7 @@ void BLIF::Reader::create_hard_block_nodes(hard_block_models* models) {
     t_model* hb_model = NULL;
     nnode_t* new_node = allocate_nnode(my_location);
 
-    // Name the node subcircuit_name~hard_block_number so that the name is unique.
     static long hard_block_number = 0;
-    odin_sprintf(buffer, "%s~%ld", subcircuit_name, hard_block_number++);
-    new_node->name = make_full_ref_name(buffer, NULL, NULL, NULL, -1);
 
     // init the edge sensitivity of hard block
     if (configuration.coarsen)
@@ -357,21 +354,15 @@ void BLIF::Reader::create_hard_block_nodes(hard_block_models* models) {
                 new_node->type = yosys_subckt_strmap[subcircuit_stripped_name];
 
             if (new_node->type == NO_OP) {
-                char new_name[READ_BLIF_BUFFER];
-                vtr::free(new_node->name);
                 /* in case of weird names, need to add memories manually */
                 int sc_spot = -1;
                 char* yosys_subckt_str = NULL;
                 if ((yosys_subckt_str = retrieve_node_type_from_subckt_name(subcircuit_stripped_name)) != NULL) {
                     /* specify node type */
                     new_node->type = yosys_subckt_strmap[yosys_subckt_str];
-                    /* specify node name */
-                    odin_sprintf(new_name, "\\%s~%ld", yosys_subckt_str, hard_block_number - 1);
                 } else if ((sc_spot = sc_lookup_string(hard_block_names, subcircuit_stripped_name)) != -1) {
                     /* specify node type */
                     new_node->type = HARD_IP;
-                    /* specify node name */
-                    odin_sprintf(new_name, "\\%s~%ld", subcircuit_stripped_name, hard_block_number - 1);
                     /* Detect used hard block for the blif generation */
                     hb_model = find_hard_block(subcircuit_stripped_name);
                     if (hb_model) {
@@ -381,7 +372,6 @@ void BLIF::Reader::create_hard_block_nodes(hard_block_models* models) {
                     error_message(PARSE_BLIF, unknown_location,
                                   "Unsupported subcircuit type (%s) in BLIF file.\n", subcircuit_name);
                 }
-                new_node->name = make_full_ref_name(new_name, NULL, NULL, NULL, -1);
 
                 // CLEAN UP
                 vtr::free(yosys_subckt_str);
@@ -493,6 +483,31 @@ void BLIF::Reader::create_hard_block_nodes(hard_block_models* models) {
             output_nets_hash->add(name, new_net);
         }
 
+        if (!configuration.coarsen
+            || !configuration.decode_names
+            || new_node->type == SPRAM
+            || new_node->type == DPRAM) {
+            // Name the node subcircuit_name~hard_block_number so that the name is unique.
+            odin_sprintf(buffer, "%s~%ld", subcircuit_name, hard_block_number++);
+            new_node->name = make_full_ref_name(buffer, NULL, NULL, NULL, -1);
+        } else {
+            // Find the basename of the output pin and name the node
+            // with BASENAME^TYPE
+            char* splitter = strrchr(new_node->output_pins[0]->net->name, '.');
+            char* output_pin_fullname = new_node->output_pins[0]->net->name;
+
+            // there is only a top module, no instantiation of submodules
+            if (splitter == NULL)
+                splitter = strchr(output_pin_fullname, '^');
+
+            char basename[READ_BLIF_BUFFER];
+            size_t basename_len = splitter - output_pin_fullname;
+
+            strncpy(basename, output_pin_fullname, basename_len);
+            basename[basename_len] = '\0';
+            new_node->name = node_name(new_node, basename);
+        }
+
         // Create a fake ast node.
         if (!configuration.coarsen || new_node->type == HARD_IP) {
             new_node->related_ast_node = create_node_w_type(HARD_BLOCK, my_location);

ODIN_II/SRC/enum_str.cpp

@@ -42,14 +42,14 @@ const char* LUTRAM_string = "lutram_ram";
 
 const char* operation_list_STR[][2] = {
     {"NO_OP", "nOP"},
+    {"CLOCK_NODE", "CLK"},
+    {"INPUT_NODE", "IN"},
+    {"OUTPUT_NODE", "OUT"},
     {"MULTI_PORT_MUX", "nMUX"}, // port 1 = control, port 2+ = mux options
     {"FF_NODE", "FF"},
     {"BUF_NODE", "BUF"},
-    {"INPUT_NODE", "IN"},
-    {"OUTPUT_NODE", "OUT"},
     {"GND_NODE", "GND"},
     {"VCC_NODE", "VCC"},
-    {"CLOCK_NODE", "CLK"},
     {"ADD", "ADD"},             // +
     {"MINUS", "MIN"},           // -
     {"BITWISE_NOT", "bNOT"},    // ~

ODIN_II/SRC/include/config_t.h

@@ -17,6 +17,7 @@ struct config_t {
     bool fflegalize;     // Legalize DFFs by making them rising edge
     bool coarsen;        // Specify if the input BLIF is coarse-grain
     bool show_yosys_log; // Print Yosys logs into the standard output stream
+    bool decode_names;   // Extracting hierarchical information from Yosys coarse-grained BLIF file for signal naming
 
     bool output_ast_graphs;     // switch that outputs ast graphs per node for use with GRaphViz tools
     bool output_netlist_graphs; // switch that outputs netlist graphs per node for use with GraphViz tools

ODIN_II/SRC/include/odin_types.h

@@ -113,6 +113,7 @@ struct global_args_t {
     argparse::ArgValue<bool> fflegalize;     // makes flip-flops rising edge sensitive
     argparse::ArgValue<bool> coarsen;        // tells Odin-II that the input blif is coarse-grain
     argparse::ArgValue<bool> show_yosys_log; // Show Yosys output logs into the standard output stream
+    argparse::ArgValue<bool> decode_names;   // Extracting hierarchical information from Yosys coarse-grained BLIF file for signal naming
 
     argparse::ArgValue<std::string> adder_def; //DEPRECATED
 
@@ -240,14 +241,14 @@ enum init_value_e {
  */
 enum operation_list {
     NO_OP,
+    CLOCK_NODE,
+    INPUT_NODE,
+    OUTPUT_NODE,
     MULTI_PORT_MUX, // port 1 = control, port 2+ = mux options
     FF_NODE,
     BUF_NODE,
-    INPUT_NODE,
-    OUTPUT_NODE,
     GND_NODE,
     VCC_NODE,
-    CLOCK_NODE,
     ADD,            // +
     MINUS,          // -
     BITWISE_NOT,    // ~

ODIN_II/SRC/netlist_statistic.cpp

@@ -478,14 +478,39 @@ void compute_statistics(netlist_t* netlist, bool display) {
         get_upward_stat(&netlist->output_node_stat, netlist->top_output_nodes, netlist->num_top_output_nodes, netlist, travelsal_id + 1);
 
         if (display) {
+            std::string hdr = "";
             printf("\n\t==== Stats ====\n");
-            for (long long op = 0; op < operation_list_END; op += 1) {
-                if (netlist->num_of_type[op] > UNUSED_NODE_TYPE) {
-                    std::string hdr = std::string("Number of <")
-                                      + operation_list_STR[op][ODIN_LONG_STRING]
-                                      + "> node: ";
-
-                    printf("%-42s%lld\n", hdr.c_str(), netlist->num_of_type[op]);
+            for (auto op = 0; op < operation_list_END; op += 1) {
+                switch (op) {
+                    // For top IO nodes generate detailed info since the design might have unconnected input nodes
+                    case INPUT_NODE: {
+                        auto unused_pi = netlist->num_top_input_nodes - netlist->num_of_type[op] - netlist->num_of_type[CLOCK_NODE];
+                        if (unused_pi > 0) {
+                            hdr = std::string("Number of unused <")
+                                  + operation_list_STR[op][ODIN_LONG_STRING]
+                                  + "> node: ";
+                            printf("%-42s%lld\n", hdr.c_str(), unused_pi);
+                        }
+                        [[fallthrough]];
+                    }
+                    case OUTPUT_NODE: {
+                        auto unused_po = netlist->num_top_output_nodes - netlist->num_of_type[op];
+                        if (unused_po > 0) {
+                            hdr = std::string("Number of unused <")
+                                  + operation_list_STR[op][ODIN_LONG_STRING]
+                                  + "> node: ";
+                            printf("%-42s%lld\n", hdr.c_str(), unused_po);
+                        }
+                        [[fallthrough]];
+                    }
+                    default: {
+                        if (netlist->num_of_type[op] > UNUSED_NODE_TYPE) {
+                            hdr = std::string("Number of <")
+                                  + operation_list_STR[op][ODIN_LONG_STRING]
+                                  + "> node: ";
+                            printf("%-42s%lld\n", hdr.c_str(), netlist->num_of_type[op]);
+                        }
+                    }
                 }
             }
             printf("%-42s%lld\n", "Total estimated number of lut: ", netlist->num_logic_element);

ODIN_II/SRC/odin_ii.cpp

@@ -533,6 +533,12 @@ void get_options(int argc, char** argv) {
         .help("TCL file")
         .metavar("TCL_FILE");
 
+    ext_elaborator_group.add_argument(global_args.decode_names, "--decode_names")
+        .help("Enable extracting hierarchical information from Yosys coarse-grained BLIF file for signal naming")
+        .default_value("false")
+        .action(argparse::Action::STORE_TRUE)
+        .metavar("DECODE_NAMES");
+
     auto& other_grp = parser.add_argument_group("other options");
 
     other_grp.add_argument(global_args.show_help, "-h")
@@ -752,6 +758,10 @@ void get_options(int argc, char** argv) {
         configuration.elaborator_type = elaborator_e::_YOSYS;
     }
 
+    if (global_args.decode_names.provenance() == argparse::Provenance::SPECIFIED) {
+        configuration.decode_names = global_args.decode_names;
+    }
+
     if (global_args.write_netlist_as_dot.provenance() == argparse::Provenance::SPECIFIED) {
         configuration.output_netlist_graphs = global_args.write_netlist_as_dot;
     }
@@ -809,6 +819,7 @@ void set_default_config() {
     configuration.coarsen = false;
     configuration.fflegalize = false;
     configuration.show_yosys_log = false;
+    configuration.decode_names = false;
     configuration.tcl_file = "";
     configuration.output_file_type = file_type_e::_BLIF;
     configuration.elaborator_type = elaborator_e::_ODIN;

doc/src/vtr/tasks.rst

@@ -144,15 +144,17 @@ Optional Fields
 
     Absolute path or relative to ``$VTR_ROOT/vtr_flow/``.
 
-    Note: Multiple _includes_dir_ are NOT allowed in a task config file.
+    Note: Multiple `includes_dir` are NOT allowed in a task config file.
 
-* **include_list_add**: A path to an _include_ file, which is relative to _includes_dir_
+* **include_list_add**: A path to an `include` file, which is relative to `includes_dir`
 
-    Multiple _include_list_add_ can be provided.
+    Multiple `include_list_add` can be provided.
 
-    _include_ files could act as the top module complementary, like definitions, macros or sub-modules.
+    `include` files could act as the top module complementary, like definitions, memory initialization files, macros or sub-modules.
+
+    Note: Only `include` files, written in supported HDLs by each frontend, are synthesized. The others are only copied to the destination folder.
 
-    Note: _include_ files will be shared among all benchmark circuits in the task config file. 
+    Note: `include` files will be shared among all benchmark circuits in the task config file. 
 
 * **pass_requirements_file**: :ref:`vtr_pass_requirements` file.
 

doc/src/yosys+odin/user_guide.rst

@@ -26,6 +26,8 @@ Synthesis Arguments
      **`--elaborator`**        **[odin (default), yosys]**       **Specify the tool that should perform the HDL elaboration**  				 	         
      **`--fflegalize`**                                          **Converts latches' sensitivity to the rising edge as required by VPR** 						 
      **`--show_yosys_log`**                                      **Showing the Yosys elaboration logs in the console window**           
+     **`--decode_names`**                                        **Enable extracting hierarchical information from Yosys coarse-grained BLIF file for signal naming \
+	 															   (the VTR flow scripts take advantage of this option by default)**
     =======================   ==============================    =================================================================================================
 
 
@@ -42,6 +44,15 @@ Passes a Verilog file to Yosys for performing elaboration.
 The BLIF elaboration and partial mapping phases will be executed on the generated netlist.
 However, all latches in the Yosys+Odin-II output file will be rising edge.
 
+.. code-block:: bash
+
+    ./odin_II --elaborator yosys -V <Path/to/Verilog/file> --decode_names
+
+
+Performs the design elaboration by Yosys parsers and generates a coarse-grained netlist in BLIF.
+Odin-II then extracts the hierarchical information of subcircuits to use for signal naming when reading the coarse-grained BLIF file.
+The BLIF elaboration and partial mapping phases will be executed on the generated netlist.
+
 .. code-block:: bash
 
     ./odin_II -b <Path/to/BLIF/file> --coarsen --fflegalize