Merge pull request #2161 from verilog-to-routing/2089_tight_floorplan_regression_test

2089 tight floorplan regression test

Author: zhaisitong

.github/workflows/test.yml

@@ -30,6 +30,7 @@ jobs:
           - {test: "vtr_reg_nightly_test2", cores: "16", options: "",          cmake: ""                                             }
           - {test: "vtr_reg_nightly_test3", cores: "16", options: "",          cmake: ""                                             }
           - {test: "vtr_reg_nightly_test4", cores: "16", options: "",          cmake: ""                                             }
+          - {test: "vtr_reg_nightly_test5", cores: "16", options: "",          cmake: ""                                             }
           - {test: "vtr_reg_strong",        cores: "16", options: "",          cmake: "-DVTR_ASSERT_LEVEL=3"                         }
           - {test: "vtr_reg_strong",        cores: "16", options: "-skip_qor", cmake: "-DVTR_ASSERT_LEVEL=3 -DVTR_ENABLE_SANITIZE=ON"}
           - {test: "vtr_reg_yosys",         cores: "16", options: "",          cmake: "-DWITH_YOSYS=ON -DYOSYS_SV_UHDM_PLUGIN=ON"    }

vtr_flow/scripts/run_vtr_flow.py

@@ -437,6 +437,9 @@ def vtr_command_argparser(prog=None):
     vpr.add_argument(
         "-sdc_file", default=None, type=str, help="Path to SDC timing constraints file."
     )
+    vpr.add_argument(
+        "-read_vpr_constraints", default=None, type=str, help="Path to vpr constraints file."
+    )
     vpr.add_argument(
         "-check_incremental_sta_consistency",
         default=False,
@@ -534,7 +537,13 @@ def vtr_command_main(arg_list, prog=None):
         vpr_args = process_unknown_args(unknown_args)
         vpr_args = process_vpr_args(args, prog, temp_dir, vpr_args)
         if args.sdc_file:
-            vpr_args["sdc_file"] = get_sdc_file(args.sdc_file, prog)
+            sdc_file_copy = get_sdc_file(args.sdc_file, prog, temp_dir)
+            vpr_args["sdc_file"] = Path(sdc_file_copy).name
+        if args.read_vpr_constraints:
+            vpr_constraint_file_copy = get_read_vpr_constraints(
+                args.read_vpr_constraints, prog, temp_dir
+            )
+            vpr_args["read_vpr_constraints"] = Path(vpr_constraint_file_copy).name
 
         print(
             args.name
@@ -581,35 +590,43 @@ def vtr_command_main(arg_list, prog=None):
         return_status = exit_status
 
     finally:
-        seconds = datetime.now() - start
+        write_vtr_summary(start, error_status, exit_status, temp_dir)
 
-        print(
-            "{status} (took {time}, "
-            "overall memory peak {stage[0]} consumed by {stage[1]} run)".format(
-                status=error_status,
-                time=vtr.format_elapsed_time(seconds),
-                stage=get_max_memory_usage(temp_dir),
-            )
-        )
-        temp_dir.mkdir(parents=True, exist_ok=True)
-        out = temp_dir / "output.txt"
-        out.touch()
-        with out.open("w") as file:
-            file.write("vpr_status=")
-            if exit_status == 0:
-                file.write("success\n")
-            else:
-                file.write("exited with return code {}\n".format(exit_status))
-            file.write(
-                "vpr_seconds=%d\nrundir=%s\nhostname=%s\nerror="
-                % (seconds.total_seconds(), str(Path.cwd()), socket.gethostname())
-            )
-            file.write("\n")
     if __name__ == "__main__":
         sys.exit(return_status)
     return return_status
 
 
+def write_vtr_summary(start, error_status, exit_status, temp_dir):
+    """
+    Write the summary of the results in vtr flow.
+    Keep 15 variable limits of pylint in function vtr_command_main.
+    """
+    seconds = datetime.now() - start
+    print(
+        "{status} (took {time}, "
+        "overall memory peak {stage[0]} consumed by {stage[1]} run)".format(
+            status=error_status,
+            time=vtr.format_elapsed_time(seconds),
+            stage=get_max_memory_usage(temp_dir),
+        )
+    )
+    temp_dir.mkdir(parents=True, exist_ok=True)
+    out = temp_dir / "output.txt"
+    out.touch()
+    with out.open("w") as file:
+        file.write("vpr_status=")
+        if exit_status == 0:
+            file.write("success\n")
+        else:
+            file.write("exited with return code {}\n".format(exit_status))
+        file.write(
+            "vpr_seconds=%d\nrundir=%s\nhostname=%s\nerror="
+            % (seconds.total_seconds(), str(Path.cwd()), socket.gethostname())
+        )
+        file.write("\n")
+
+
 def process_unknown_args(unknown_args):
     """
     We convert the unknown_args into a dictionary, which is eventually
@@ -738,17 +755,30 @@ def process_vpr_args(args, prog, temp_dir, vpr_args):
     return vpr_args
 
 
-def get_sdc_file(sdc_file, prog):
+def get_sdc_file(sdc_file, prog, temp_dir):
     """
     takes in the sdc_file and returns a path to that file if it exists.
     """
-    if not Path(sdc_file).exists():
-        if sdc_file.startswith("/"):
-            sdc_file = Path(str(Path(prog).parent.parent) + sdc_file)
-        else:
-            sdc_file = Path(prog).parent.parent / sdc_file
+    if not sdc_file.startswith("/"):
+        sdc_file = Path(prog).parent.parent / sdc_file
+    sdc_file_name = Path(sdc_file).name
+    sdc_file_copy = Path(temp_dir) / Path(sdc_file_name)
+    shutil.copy(str(sdc_file), str(sdc_file_copy))
+
+    return str(vtr.verify_file(sdc_file_copy, "sdc file"))
+
+
+def get_read_vpr_constraints(read_vpr_constraints, prog, temp_dir):
+    """
+    takes in the read_vpr_constraints and returns a path to that file if it exists.
+    """
+    if not read_vpr_constraints.startswith("/"):
+        read_vpr_constraints = Path(prog).parent.parent / read_vpr_constraints
+    vpr_constraint_file_name = Path(read_vpr_constraints).name
+    vpr_constraint_file_copy = Path(temp_dir) / Path(vpr_constraint_file_name)
+    shutil.copy(str(read_vpr_constraints), str(vpr_constraint_file_copy))
 
-    return str(vtr.verify_file(sdc_file, "sdc file"))
+    return str(vtr.verify_file(vpr_constraint_file_copy, "vpr constraint file"))
 
 
 def except_vtr_error(error, expect_fail, verbose):

vtr_flow/sdc/samples/neuron_stratixiv_arch_timing.sdc

@@ -0,0 +1,71 @@
+#VPR compatible SDC file for benchmark circuit 'neuron'
+
+# Creates an external virtual clock 'virtual_io_clock', and non-virtual clocks for each netlist clock (each with 1ns target clock period).
+# Paths between netlist clock domains are not analyzed, but paths to/from the 'virtual_io_clock' and netlist clocks are analyzed.
+# Small clocks which drive less than 0.1% of blocks are ignored and not created
+
+#**************************************************************
+# Unit Information
+#**************************************************************
+#VPR assumes time unit is nanoseconds
+
+#**************************************************************
+# Create Clock
+#**************************************************************
+create_clock -period 1.000 -name virtual_io_clock
+create_clock -period 1.000 {clk_clk}
+
+#**************************************************************
+# Create Generated Clock
+#**************************************************************
+#None
+
+#**************************************************************
+# Set Clock Latency
+#**************************************************************
+set_clock_latency -source 0.000 [get_clocks {clk_clk}]
+
+#**************************************************************
+# Set Clock Uncertainty
+#**************************************************************
+set_clock_uncertainty -from [get_clocks {clk_clk}] -to [get_clocks {clk_clk}] 0.000
+set_clock_uncertainty -from [get_clocks {clk_clk}] -to [get_clocks {virtual_io_clock}] 0.000
+set_clock_uncertainty -from [get_clocks {virtual_io_clock}] -to [get_clocks {clk_clk}] 0.000
+set_clock_uncertainty -from [get_clocks {virtual_io_clock}] -to [get_clocks {virtual_io_clock}] 0.000
+
+#**************************************************************
+# Set Input Delay
+#**************************************************************
+set_input_delay -clock virtual_io_clock 0.0 [get_ports *]
+
+#**************************************************************
+# Set Output Delay
+#**************************************************************
+set_output_delay -clock virtual_io_clock 0.0 [get_ports *]
+
+#**************************************************************
+# Set Clock Groups
+#**************************************************************
+#None
+
+#**************************************************************
+# Set False Path
+#**************************************************************
+#None
+
+#**************************************************************
+# Set Multicycle Path
+#**************************************************************
+#None
+
+#**************************************************************
+# Set Maximum Delay
+#**************************************************************
+#None
+
+#**************************************************************
+# Set Minimum Delay
+#**************************************************************
+#None
+
+#EOF

vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/task_list.txt

@@ -14,5 +14,4 @@ regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/open_cores_frac
 regression_tests/vtr_reg_nightly_test1/symbiflow
 regression_tests/vtr_reg_nightly_test1/power_extended_arch_list
 regression_tests/vtr_reg_nightly_test1/power_extended_circuit_list
-regression_tests/vtr_reg_nightly_test1/vpr_ispd
 

vtr_flow/tasks/regression_tests/vtr_reg_nightly_test5/task_list.txt

@@ -0,0 +1,2 @@
+regression_tests/vtr_reg_nightly_test5/vpr_ispd
+regression_tests/vtr_reg_nightly_test5/vpr_tight_floorplan

…nightly_test1/vpr_ispd/config/config.txt …nightly_test5/vpr_ispd/config/config.txtvtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vpr_ispd/config/config.txt renamed to vtr_flow/tasks/regression_tests/vtr_reg_nightly_test5/vpr_ispd/config/config.txt vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vpr_ispd/config/config.txt renamed to vtr_flow/tasks/regression_tests/vtr_reg_nightly_test5/vpr_ispd/config/config.txt

@@ -0,0 +1,30 @@
+##############################################
+# Configuration file for running experiments
+##############################################
+
+# Path to directory of circuits to use
+circuits_dir=tasks/regression_tests/vtr_reg_nightly_test5/vpr_tight_floorplan
+
+# Path to directory of architectures to use
+archs_dir=tasks/regression_tests/vtr_reg_nightly_test5/vpr_tight_floorplan
+
+# Add circuits to list to sweep
+circuit_list_add=neuron_stratixiv_arch_timing.blif
+
+# Add architectures to list to sweep
+arch_list_add=stratixiv_arch_neuron.timing.xml
+
+# Parse info and how to parse
+parse_file=vpr_standard.txt
+
+# How to parse QoR info
+qor_parse_file=qor_standard.txt
+
+# Pass requirements
+pass_requirements_file=pass_requirements.txt
+
+# Script parameters
+script_params_common =-starting_stage vpr --route_chan_width 300 --max_router_iterations 400 --router_lookahead map --initial_pres_fac 1.0 --router_profiler_astar_fac 1.5 --seed 3 --device neuron 
+script_params_list_add = -sdc_file sdc/samples/neuron_stratixiv_arch_timing.sdc -read_vpr_constraints tasks/regression_tests/vtr_reg_nightly_test5/vpr_tight_floorplan/sixteenth.xml
+script_params_list_add = -sdc_file sdc/samples/neuron_stratixiv_arch_timing.sdc -read_vpr_constraints tasks/regression_tests/vtr_reg_nightly_test5/vpr_tight_floorplan/half_blocks_half.xml
+script_params_list_add = -sdc_file sdc/samples/neuron_stratixiv_arch_timing.sdc -read_vpr_constraints tasks/regression_tests/vtr_reg_nightly_test5/vpr_tight_floorplan/one_big_partition.xml

…test1/vpr_ispd/config/golden_results.txt …test5/vpr_ispd/config/golden_results.txtvtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vpr_ispd/config/golden_results.txt renamed to vtr_flow/tasks/regression_tests/vtr_reg_nightly_test5/vpr_ispd/config/golden_results.txt vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vpr_ispd/config/golden_results.txt renamed to vtr_flow/tasks/regression_tests/vtr_reg_nightly_test5/vpr_ispd/config/golden_results.txt

@@ -0,0 +1,4 @@
+arch	circuit	script_params	vtr_flow_elapsed_time	vtr_max_mem_stage	vtr_max_mem	error	odin_synth_time	max_odin_mem	yosys_synth_time	max_yosys_mem	abc_depth	abc_synth_time	abc_cec_time	abc_sec_time	max_abc_mem	ace_time	max_ace_mem	num_clb	num_io	num_memories	num_mult	vpr_status	vpr_revision	vpr_build_info	vpr_compiler	vpr_compiled	hostname	rundir	max_vpr_mem	num_primary_inputs	num_primary_outputs	num_pre_packed_nets	num_pre_packed_blocks	num_netlist_clocks	num_post_packed_nets	num_post_packed_blocks	device_width	device_height	device_grid_tiles	device_limiting_resources	device_name	pack_mem	pack_time	placed_wirelength_est	place_mem	place_time	place_quench_time	placed_CPD_est	placed_setup_TNS_est	placed_setup_WNS_est	placed_geomean_nonvirtual_intradomain_critical_path_delay_est	place_delay_matrix_lookup_time	place_quench_timing_analysis_time	place_quench_sta_time	place_total_timing_analysis_time	place_total_sta_time	min_chan_width	routed_wirelength	min_chan_width_route_success_iteration	logic_block_area_total	logic_block_area_used	min_chan_width_routing_area_total	min_chan_width_routing_area_per_tile	min_chan_width_route_time	min_chan_width_total_timing_analysis_time	min_chan_width_total_sta_time	crit_path_routed_wirelength	crit_path_route_success_iteration	crit_path_total_nets_routed	crit_path_total_connections_routed	crit_path_total_heap_pushes	crit_path_total_heap_pops	critical_path_delay	geomean_nonvirtual_intradomain_critical_path_delay	setup_TNS	setup_WNS	hold_TNS	hold_WNS	crit_path_routing_area_total	crit_path_routing_area_per_tile	router_lookahead_computation_time	crit_path_route_time	crit_path_total_timing_analysis_time	crit_path_total_sta_time	
+stratixiv_arch_neuron.timing.xml	neuron_stratixiv_arch_timing.blif	common_-sdc_file_sdc/samples/neuron_stratixiv_arch_timing.sdc_-read_vpr_constraints_tasks/regression_tests/vtr_reg_nightly_test5/vpr_tight_floorplan/sixteenth.xml	799.39	vpr	2.92 GiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	42	-1	-1	success	v8.0.0-6558-g07167c26e	release IPO VTR_ASSERT_LEVEL=2	GNU 11.2.0 on Linux-5.15.0-50-generic x86_64	2022-10-14T23:49:48	virtual	/home/zhaisitong/worksapce/vtr2/vtr-verilog-to-routing/vtr_flow/tasks	3062716	42	35	119888	86875	1	51809	3567	129	96	12384	-1	neuron	2030.2 MiB	224.15	597383	2910.1 MiB	152.46	0.81	7.61685	-74849.5	-6.61685	5.08623	58.44	0.262079	0.232955	50.6768	43.2043	-1	772505	48	0	0	2.28642e+08	18462.7	65.52	80.6627	70.338	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	
+stratixiv_arch_neuron.timing.xml	neuron_stratixiv_arch_timing.blif	common_-sdc_file_sdc/samples/neuron_stratixiv_arch_timing.sdc_-read_vpr_constraints_tasks/regression_tests/vtr_reg_nightly_test5/vpr_tight_floorplan/half_blocks_half.xml	674.41	vpr	2.73 GiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	42	-1	-1	success	v8.0.0-6558-g07167c26e	release IPO VTR_ASSERT_LEVEL=2	GNU 11.2.0 on Linux-5.15.0-50-generic x86_64	2022-10-14T23:49:48	virtual	/home/zhaisitong/worksapce/vtr2/vtr-verilog-to-routing/vtr_flow/tasks	2864032	42	35	119888	86875	1	51282	3422	129	96	12384	-1	neuron	1830.1 MiB	112.49	596408	2717.5 MiB	158.00	0.72	8.25008	-74642.4	-7.25008	5.56231	59.35	0.274684	0.232207	53.3837	45.3298	-1	773463	30	0	0	2.28642e+08	18462.7	52.31	73.4046	63.5131	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	
+stratixiv_arch_neuron.timing.xml	neuron_stratixiv_arch_timing.blif	common_-sdc_file_sdc/samples/neuron_stratixiv_arch_timing.sdc_-read_vpr_constraints_tasks/regression_tests/vtr_reg_nightly_test5/vpr_tight_floorplan/one_big_partition.xml	651.65	vpr	2.73 GiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	42	-1	-1	success	v8.0.0-6558-g07167c26e	release IPO VTR_ASSERT_LEVEL=2	GNU 11.2.0 on Linux-5.15.0-50-generic x86_64	2022-10-14T23:49:48	virtual	/home/zhaisitong/worksapce/vtr2/vtr-verilog-to-routing/vtr_flow/tasks	2866000	42	35	119888	86875	1	51283	3425	129	96	12384	-1	neuron	1832.1 MiB	115.72	596968	2719.5 MiB	121.72	0.80	8.38198	-70951.7	-7.38198	5.24439	61.07	0.276509	0.233816	40.1409	34.0809	-1	770923	29	0	0	2.28642e+08	18462.7	54.69	59.6691	51.82	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1