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vaughnbetzvaughnbetz
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Merge pull request #2185 from byuccl/graphics_fix
Fix for Dangling Interconnect and removal of fully unidirectional/bidirectional arch
2 parents 9d97e94 + 4b9632a commit 3c1ea08

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4 files changed

+26
-37
lines changed

4 files changed

+26
-37
lines changed

‎vpr/src/draw/draw_basic.cpp‎

Lines changed: 6 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -641,21 +641,18 @@ void draw_partial_route(const std::vector<int>& rr_nodes_to_draw, ezgl::renderer
641641
if (draw_state->draw_route_type == GLOBAL)
642642
chanx_track[rr_graph.node_xlow(rr_node)][rr_graph.node_ylow(rr_node)]++;
643643

644-
int itrack = get_track_num(inode, chanx_track, chany_track);
645644
draw_rr_chan(inode, draw_state->draw_rr_node[inode].color, g);
646645

647646
switch (prev_type) {
648647
case CHANX: {
649648
draw_chanx_to_chanx_edge(RRNodeId(prev_node), RRNodeId(inode),
650-
itrack, switch_type, g);
649+
switch_type, g);
651650
break;
652651
}
653652
case CHANY: {
654-
int prev_track = get_track_num(prev_node, chanx_track,
655-
chany_track);
656-
draw_chanx_to_chany_edge(inode, itrack, prev_node,
653+
draw_chanx_to_chany_edge(inode, prev_node,
657654

658-
prev_track, FROM_Y_TO_X, switch_type, g);
655+
FROM_Y_TO_X, switch_type, g);
659656
break;
660657
}
661658
case OPIN: {
@@ -675,20 +672,17 @@ void draw_partial_route(const std::vector<int>& rr_nodes_to_draw, ezgl::renderer
675672
if (draw_state->draw_route_type == GLOBAL)
676673
chany_track[rr_graph.node_xlow(rr_node)][rr_graph.node_ylow(rr_node)]++;
677674

678-
int itrack = get_track_num(inode, chanx_track, chany_track);
679675
draw_rr_chan(inode, draw_state->draw_rr_node[inode].color, g);
680676

681677
switch (prev_type) {
682678
case CHANX: {
683-
int prev_track = get_track_num(prev_node, chanx_track,
684-
chany_track);
685-
draw_chanx_to_chany_edge(prev_node, prev_track, inode,
686-
itrack, FROM_X_TO_Y, switch_type, g);
679+
draw_chanx_to_chany_edge(prev_node, inode,
680+
FROM_X_TO_Y, switch_type, g);
687681
break;
688682
}
689683
case CHANY: {
690684
draw_chany_to_chany_edge(RRNodeId(prev_node), RRNodeId(inode),
691-
itrack, switch_type, g);
685+
switch_type, g);
692686
break;
693687
}
694688
case OPIN: {

‎vpr/src/draw/draw_rr.cpp‎

Lines changed: 7 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -297,7 +297,7 @@ void draw_rr_edges(int inode, ezgl::renderer* g) {
297297
auto rr_node = RRNodeId(inode);
298298

299299
t_rr_type from_type, to_type;
300-
int to_node, from_ptc_num, to_ptc_num;
300+
int to_node;
301301
short switch_type;
302302

303303
from_type = rr_graph.node_type(rr_node);
@@ -308,12 +308,9 @@ void draw_rr_edges(int inode, ezgl::renderer* g) {
308308
return; /* Nothing to draw. */
309309
}
310310

311-
from_ptc_num = rr_graph.node_ptc_num(rr_node);
312-
313311
for (t_edge_size iedge = 0, l = rr_graph.num_edges(RRNodeId(inode)); iedge < l; iedge++) {
314312
to_node = size_t(rr_graph.edge_sink_node(rr_node, iedge));
315313
to_type = rr_graph.node_type(RRNodeId(to_node));
316-
to_ptc_num = rr_graph.node_ptc_num(RRNodeId(to_node));
317314
bool edge_configurable = rr_graph.edge_is_configurable(RRNodeId(inode), iedge);
318315

319316
switch (from_type) {
@@ -396,7 +393,7 @@ void draw_rr_edges(int inode, ezgl::renderer* g) {
396393
}
397394
switch_type = rr_graph.edge_switch(rr_node, iedge);
398395
draw_chanx_to_chanx_edge(rr_node, RRNodeId(to_node),
399-
to_ptc_num, switch_type, g);
396+
switch_type, g);
400397
break;
401398

402399
case CHANY:
@@ -412,8 +409,8 @@ void draw_rr_edges(int inode, ezgl::renderer* g) {
412409
g->set_color(blk_DARKGREEN);
413410
}
414411
switch_type = rr_graph.edge_switch(rr_node, iedge);
415-
draw_chanx_to_chany_edge(inode, from_ptc_num, to_node,
416-
to_ptc_num, FROM_X_TO_Y, switch_type, g);
412+
draw_chanx_to_chany_edge(inode, to_node,
413+
FROM_X_TO_Y, switch_type, g);
417414
break;
418415

419416
default:
@@ -465,8 +462,8 @@ void draw_rr_edges(int inode, ezgl::renderer* g) {
465462
g->set_color(blk_DARKGREEN);
466463
}
467464
switch_type = rr_graph.edge_switch(rr_node, iedge);
468-
draw_chanx_to_chany_edge(to_node, to_ptc_num, inode,
469-
from_ptc_num, FROM_Y_TO_X, switch_type, g);
465+
draw_chanx_to_chany_edge(to_node, inode,
466+
FROM_Y_TO_X, switch_type, g);
470467
break;
471468

472469
case CHANY:
@@ -484,7 +481,7 @@ void draw_rr_edges(int inode, ezgl::renderer* g) {
484481
}
485482
switch_type = rr_graph.edge_switch(rr_node, iedge);
486483
draw_chany_to_chany_edge(rr_node, RRNodeId(to_node),
487-
to_ptc_num, switch_type, g);
484+
switch_type, g);
488485
break;
489486

490487
default:

‎vpr/src/draw/draw_rr_edges.cpp‎

Lines changed: 10 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -54,7 +54,7 @@
5454
# include <X11/keysym.h>
5555
# endif
5656

57-
void draw_chany_to_chany_edge(RRNodeId from_node, RRNodeId to_node, int to_track, short switch_type, ezgl::renderer* g) {
57+
void draw_chany_to_chany_edge(RRNodeId from_node, RRNodeId to_node, short switch_type, ezgl::renderer* g) {
5858
t_draw_state* draw_state = get_draw_state_vars();
5959
t_draw_coords* draw_coords = get_draw_coords_vars();
6060
auto& device_ctx = g_vpr_ctx.device();
@@ -100,7 +100,7 @@ void draw_chany_to_chany_edge(RRNodeId from_node, RRNodeId to_node, int to_track
100100
/* UDSD Modification by WMF Begin */
101101
else {
102102
if (rr_graph.node_direction(to_node) != Direction::BIDIR) {
103-
if (to_track % 2 == 0) { /* INC wire starts at bottom edge */
103+
if (rr_graph.node_direction(to_node) == Direction::INC) { /* INC wire starts at bottom edge */
104104

105105
y2 = to_chan.bottom();
106106
/* since no U-turns from_track must be INC as well */
@@ -144,7 +144,7 @@ void draw_chany_to_chany_edge(RRNodeId from_node, RRNodeId to_node, int to_track
144144
}
145145
}
146146

147-
void draw_chanx_to_chanx_edge(RRNodeId from_node, RRNodeId to_node, int to_track, short switch_type, ezgl::renderer* g) {
147+
void draw_chanx_to_chanx_edge(RRNodeId from_node, RRNodeId to_node, short switch_type, ezgl::renderer* g) {
148148
/* Draws a connection between two x-channel segments. Passing in the track *
149149
* numbers allows this routine to be used for both rr_graph and routing *
150150
* drawing-> */
@@ -191,7 +191,7 @@ void draw_chanx_to_chanx_edge(RRNodeId from_node, RRNodeId to_node, int to_track
191191
else {
192192
if (rr_graph.node_direction(to_node) != Direction::BIDIR) {
193193
/* must connect to to_node's wire beginning at x2 */
194-
if (to_track % 2 == 0) { /* INC wire starts at leftmost edge */
194+
if (rr_graph.node_direction(to_node) == Direction::INC) { /* INC wire starts at leftmost edge */
195195
VTR_ASSERT(from_xlow < to_xlow);
196196
x2 = to_chan.left();
197197
/* since no U-turns from_track must be INC as well */
@@ -236,7 +236,7 @@ void draw_chanx_to_chanx_edge(RRNodeId from_node, RRNodeId to_node, int to_track
236236
}
237237
}
238238

239-
void draw_chanx_to_chany_edge(int chanx_node, int chanx_track, int chany_node, int chany_track, enum e_edge_dir edge_dir, short switch_type, ezgl::renderer* g) {
239+
void draw_chanx_to_chany_edge(int chanx_node, int chany_node, enum e_edge_dir edge_dir, short switch_type, ezgl::renderer* g) {
240240
t_draw_state* draw_state = get_draw_state_vars();
241241
t_draw_coords* draw_coords = get_draw_coords_vars();
242242
auto& device_ctx = g_vpr_ctx.device();
@@ -259,6 +259,7 @@ void draw_chanx_to_chany_edge(int chanx_node, int chanx_track, int chany_node, i
259259
y1 = chanx_bbox.bottom();
260260
x2 = chany_bbox.left();
261261

262+
// these values xhigh/low yhigh/low mark the cordinates for the begining and ends of the wire.
262263
chanx_xlow = rr_graph.node_xlow(RRNodeId(chanx_node));
263264
chanx_y = rr_graph.node_ylow(RRNodeId(chanx_node));
264265
chany_x = rr_graph.node_xlow(RRNodeId(chany_node));
@@ -267,26 +268,23 @@ void draw_chanx_to_chany_edge(int chanx_node, int chanx_track, int chany_node, i
267268
if (chanx_xlow <= chany_x) { /* Can draw connection going right */
268269
/* Connection not at end of the CHANX segment. */
269270
x1 = draw_coords->tile_x[chany_x] + draw_coords->get_tile_width();
270-
271-
if (rr_graph.node_direction(RRNodeId(chanx_node)) != Direction::BIDIR) {
271+
if (rr_graph.node_direction(RRNodeId(chanx_node)) != Direction::BIDIR && (SwitchType)switch_type != SwitchType::SHORT) {
272272
if (edge_dir == FROM_X_TO_Y) {
273-
if ((chanx_track % 2) == 1) { /* If dec wire, then going left */
273+
if (rr_graph.node_direction(RRNodeId(chanx_node)) == Direction::DEC) { /* If dec wire, then going left */
274274
x1 = draw_coords->tile_x[chany_x + 1];
275275
}
276276
}
277277
}
278-
279278
} else { /* Must draw connection going left. */
280279
x1 = chanx_bbox.left();
281280
}
282-
283281
if (chany_ylow <= chanx_y) { /* Can draw connection going up. */
284282
/* Connection not at end of the CHANY segment. */
285283
y2 = draw_coords->tile_y[chanx_y] + draw_coords->get_tile_width();
286284

287-
if (rr_graph.node_direction(RRNodeId(chany_node)) != Direction::BIDIR) {
285+
if (rr_graph.node_direction(RRNodeId(chany_node)) != Direction::BIDIR && (SwitchType)switch_type != SwitchType::SHORT) {
288286
if (edge_dir == FROM_Y_TO_X) {
289-
if ((chany_track % 2) == 1) { /* If dec wire, then going down */
287+
if (rr_graph.node_direction(RRNodeId(chany_node)) == Direction::DEC) { /* If dec wire, then going down */
290288
y2 = draw_coords->tile_y[chanx_y + 1];
291289
}
292290
}

‎vpr/src/draw/draw_rr_edges.h‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -47,9 +47,9 @@
4747
# include "place_macro.h"
4848
# include "buttons.h"
4949

50-
void draw_chany_to_chany_edge(RRNodeId from_node, RRNodeId to_node, int to_track, short switch_type, ezgl::renderer* g);
51-
void draw_chanx_to_chanx_edge(RRNodeId from_node, RRNodeId to_node, int to_track, short switch_type, ezgl::renderer* g);
52-
void draw_chanx_to_chany_edge(int chanx_node, int chanx_track, int chany_node, int chany_track, enum e_edge_dir edge_dir, short switch_type, ezgl::renderer* g);
50+
void draw_chany_to_chany_edge(RRNodeId from_node, RRNodeId to_node, short switch_type, ezgl::renderer* g);
51+
void draw_chanx_to_chanx_edge(RRNodeId from_node, RRNodeId to_node, short switch_type, ezgl::renderer* g);
52+
void draw_chanx_to_chany_edge(int chanx_node, int chany_node, enum e_edge_dir edge_dir, short switch_type, ezgl::renderer* g);
5353
void draw_pin_to_pin(int opin, int ipin, ezgl::renderer* g);
5454
void draw_pin_to_sink(int ipin_node, int sink_node, ezgl::renderer* g);
5555
void draw_source_to_pin(int source_node, int opin_node, ezgl::renderer* g);

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