Merge remote-tracking branch 'upstream/master' into graphics_fix

Author: WhiteNinjaZ

.github/workflows/test.yml

@@ -31,6 +31,7 @@ jobs:
           - {test: "vtr_reg_nightly_test3", cores: "16", options: "",          cmake: "",                                              extra_pkgs: ""}
           - {test: "vtr_reg_nightly_test4", cores: "16", options: "",          cmake: "",                                              extra_pkgs: ""}
           - {test: "vtr_reg_nightly_test5", cores: "16", options: "",          cmake: "",                                              extra_pkgs: ""}
+          - {test: "vtr_reg_nightly_test6", cores: "16", options: "",          cmake: "-DODIN_USE_YOSYS=ON",                           extra_pkgs: ""}
           - {test: "vtr_reg_strong",        cores: "16", options: "",          cmake: "-DVTR_ASSERT_LEVEL=3",                          extra_pkgs: "libeigen3-dev"}
           - {test: "vtr_reg_strong",        cores: "16", options: "-skip_qor", cmake: "-DVTR_ASSERT_LEVEL=3 -DVTR_ENABLE_SANITIZE=ON", extra_pkgs: "libeigen3-dev"}
           - {test: "vtr_reg_yosys",         cores: "16", options: "",          cmake: "-DWITH_YOSYS=ON -DYOSYS_SV_UHDM_PLUGIN=ON",     extra_pkgs: ""}

ODIN_II/regression_test/benchmark/task/koios/synthesis_result.json

@@ -24,7 +24,8 @@ circuits_dir=../../../../vtr_flow/benchmarks/verilog/koios
 #-------------------------------------------------------
 # specify the benchmarks
 #-------------------------------------------------------
-circuit_list_add=tpu_like.small.v
+circuit_list_add=tpu_like.small.os.v
+circuit_list_add=tpu_like.small.ws.v
 circuit_list_add=dla_like.small.v
 circuit_list_add=bnn.v
 circuit_list_add=attention_layer.v
@@ -45,10 +46,10 @@ includes_dir=../../../../vtr_flow/benchmarks/verilog/koios
 #-------------------------------------------------------
 # specify the include files
 #-------------------------------------------------------
-# Some benchmarks instantiate complex dsp blocks to implement features
-# like native floating point math, cascade chains, etc. This functionality
-# is guarded under the `complex_dsp` macro. The complex_dsp_include.v file 
-# defines this macro, thereby enabling instantiations of the complex dsp.
-include_list_add=complex_dsp_include.v
+# Some benchmarks instantiate hard dsp and memory blocks 
+# This functionality is guarded under the `complex_dsp` and `hard_mem` macros. 
+# The hard_block_include.v file 
+# defines this macros, thereby enabling instantiations of the hard blocks
+include_list_add=hard_block_include.v
 
 synthesis_parse_file=regression_test/parse_result/conf/synth.toml

ODIN_II/regression_test/benchmark/task/koios/task.conf

@@ -25,18 +25,20 @@ circuits_dir=../vtr_flow/benchmarks/verilog/koios
 #-------------------------------------------------------
 # specify the benchmarks
 #-------------------------------------------------------
-circuit_list_add=tpu_like.small.v
+circuit_list_add=tpu_like.small.os.v
+circuit_list_add=tpu_like.small.ws.v
 circuit_list_add=dla_like.small.v
 circuit_list_add=bnn.v
 circuit_list_add=attention_layer.v
 circuit_list_add=conv_layer_hls.v
 circuit_list_add=conv_layer.v
 circuit_list_add=gemm_layer.v
-circuit_list_add=eltwise_layer.v
-circuit_list_add=robot_rl.v
-circuit_list_add=reduction_layer.v
-circuit_list_add=spmv.v
-circuit_list_add=softmax.v
+circuit_list_add=bwave_like.fixed.small.v
+circuit_list_add=bwave_like.fixed.large.v
+circuit_list_add=bwave_like.float.small.v
+circuit_list_add=bwave_like.float.large.v
+circuit_list_add=proxy.5.v
+circuit_list_add=proxy.8.v
 
 #-------------------------------------------------------
 # specify the directory to look for include file in
@@ -46,10 +48,10 @@ includes_dir=../vtr_flow/benchmarks/verilog/koios
 #-------------------------------------------------------
 # specify the include files
 #-------------------------------------------------------
-# Some benchmarks instantiate complex dsp blocks to implement features
-# like native floating point math, cascade chains, etc. This functionality
-# is guarded under the `complex_dsp` macro. The complex_dsp_include.v file 
-# defines this macro, thereby enabling instantiations of the complex dsp.
-include_list_add=complex_dsp_include.v
+# Some benchmarks instantiate hard dsp and memory blocks 
+# This functionality is guarded under the `complex_dsp` and `hard_mem` macros. 
+# The hard_block_include.v file 
+# defines this macros, thereby enabling instantiations of the hard blocks
+include_list_add=hard_block_include.v
 
 synthesis_parse_file=regression_test/parse_result/conf/synth.toml

ODIN_II/regression_test/benchmark/task/yosys+odin/koios/synthesis_result.json

@@ -64,11 +64,11 @@ The Titan benchmarks are suitable for large-scale FPGA CAD research, and FPGA ar
 
 .. seealso:: :ref:`titan_benchmarks_tutorial`
 
-Koios Benchmarks
+Koios 2.0 Benchmarks
 -----------------
 The Koios benchmarks :cite:`koios_benchmarks` are a set of Deep Learning (DL) benchmarks.
 They are suitable for DL related architecture and CAD research.
-There are 19 designs that include several medium-sized benchmarks and some large benchmarks.
+There are 40 designs that include several medium-sized benchmarks and some large benchmarks.
 The designs target different network types (CNNs, RNNs, MLPs, RL) and layer types (fully-connected, convolution, activation, softmax, reduction, eltwise).
 Some of the designs are generated from HLS tools as well.
 These designs use many precisions including binary, different fixed point types int8/16/32, brain floating point (bfloat16), and IEEE half-precision floating point (fp16).
@@ -80,21 +80,26 @@ These designs use many precisions including binary, different fixed point types
     =================   ======================================
     Benchmark           Description
     =================   ======================================
-    clstm_like          CLSTM-like accelerator
     dla_like            Intel-DLA-like accelerator
+    clstm_like          CLSTM-like accelerator
+    deepfreeze          ARM FixyNN design
+    tdarknet_like       Accelerator for Tiny Darknet
+    bwave_like          Microsoft-Brainwave-like design
     lstm                LSTM engine
-    tpu_like            Google-TPU-v1-like accelerator
     bnn                 4-layer binary neural network
-    tiny_darknet_like   Accelerator for Tiny Darknet
+    lenet               Accelerator for LeNet-5
+    dnnweaver           DNNWeaver accelerator
+    tpu_like            Google-TPU-v1-like accelerator
     gemm_layer          20x20 matrix multiplication engine
     attention_layer     Transformer self-attention layer
     conv_layer          GEMM based convolution
-    spmv                Sparse matrix vector multiplication
     robot_rl            Robot+maze application
     reduction_layer     Add/max/min reduction tree
+    spmv                Sparse matrix vector multiplication
+    eltwise_layer       Matrix elementwise add/sub/mult
     softmax             Softmax classification layer
     conv_layer_hls      Sliding window convolution
-    eltwise_layer       Matrix elementwise add/sub/mult
+    proxy               Proxy/synthetic benchmarks
     =================   ======================================
 
 The VTR benchmarks are provided as Verilog (enabling full flexibility to modify and change how the designs are implemented) under: ::