VerilLean: A Lean-embedded framework to verify Verilog modules

TBA

Name		Name	Last commit message	Last commit date
Latest commit History 9 Commits
.github/workflows		.github/workflows
VerilLean		VerilLean
.gitignore		.gitignore
Main.lean		Main.lean
README.md		README.md
VerilLean.lean		VerilLean.lean
lake-manifest.json		lake-manifest.json
lakefile.toml		lakefile.toml
lean-toolchain		lean-toolchain

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