Veritune

A digital phase vocoder in Verilog

Authors

This project targets the Nexys-2, a Spartan 3E board.

Full source on Github

Name		Name	Last commit message	Last commit date
Latest commit History 46 Commits
report		report
.gitignore		.gitignore
FFT1024.v		FFT1024.v
FFT1024_LUT.v		FFT1024_LUT.v
FFT1024_LUT_tb.v		FFT1024_LUT_tb.v
FFT1024_synth_test.v		FFT1024_synth_test.v
FFT1024_tb.v		FFT1024_tb.v
FFT4.v		FFT4.v
FFT4_LUT.v		FFT4_LUT.v
FFT4_LUT_tb.v		FFT4_LUT_tb.v
FFT4_tb.v		FFT4_tb.v
FFT8.v		FFT8.v
FFT8_LUT.v		FFT8_LUT.v
HANN_LUT.v		HANN_LUT.v
IFFT1024_tb_v.v		IFFT1024_tb_v.v
dualport_ram.v		dualport_ram.v
ee201_debounce_DPB_SCEN_CCEN_MCEN.v		ee201_debounce_DPB_SCEN_CCEN_MCEN.v
ee201_fft_proto.m		ee201_fft_proto.m
ee201_sequential_FFT.m		ee201_sequential_FFT.m
fft_butterfly_unit.v		fft_butterfly_unit.v
fft_pointers.v		fft_pointers.v
fft_sm.v		fft_sm.v
fft_sm_initial_lut.v		fft_sm_initial_lut.v
fft_sm_tb.v		fft_sm_tb.v
fft_split_tb.v		fft_split_tb.v
fft_top.ucf		fft_top.ucf
fft_top.v		fft_top.v
frames.v		frames.v
in.txt		in.txt
proposal.tex		proposal.tex
readme.md		readme.md
shifter.v		shifter.v
ssdhex.v		ssdhex.v
veritune.m		veritune.m
veritune_sm.v		veritune_sm.v
veritune_top.ucf		veritune_top.ucf
veritune_top.v		veritune_top.v