A High-performance Timing Analysis Tool for VLSI Systems

Standard Cell Library based Memory Compiler using FF/Latch cells

GDSII File Parsing, IC Layout Analysis, and Parameter Extraction

A Standalone Structural Verilog Parser

VLSI EDA Global Router

Library of approximate arithmetic circuits

A Fast C++ Header-only Parser for Standard Parasitic Exchange Format (SPEF).

Electrical And Electronic Engineering Course Materials

This is this VLSI designing Project. This Project is created in Cadence Virtuoso. See the PDF for Pre-Post layout results and other details

Selected problems and their solutions from the book on "Machine Intelligence in Design Automation"

All the projects and assignments done as part of VLSI course.

genetic algorithm usage for routing optimization ( pyqt )

Simplify VLSI (timing, power, noise, correlation, reliability) modeling and analysis with Characterization Description Format

This paper presents an intelligent sizing method to improve the performance and efficiency of a CMOS Ring Oscillator (RO). The proposed approach is based on the simultaneous utilization of powerful and new multi-objective optimization techniques along with a circuit simulator under a data link. The proposed optimizing tool creates a perfect trad…

Given A and B are 64-bit inputs. With two selection lines s1 and s0 to perform the operations, A+B, A-B, AB, C+AB using Baugh Wooley multiplier

VLSI Design, Magic, OpenCircuitDesign,CMOS VLSI Design, CMOS Inverter Magic

VLSI Physical Design

Some ramblings about my major. 一些有关我的专业的碎碎念

delay estimation, sequencing, power dissipation of digital circuits

Designed and simulated all fundamental and universal CMOS logic gates (NOT, AND, OR, NAND, NOR, XOR, XNOR) using the Electric VLSI Design Tool. This project includes schematic design, DRC-clean layouts, ALS simulation, and waveform analysis.