5-Stage Pipelined RISC-V CPU + Custom Compiler
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Updated
Mar 6, 2026 - C++
5-Stage Pipelined RISC-V CPU + Custom Compiler
Risc-V 32i processor written in the Verilog HDL
FISC V— Fundamental Instruction Set Computer
RV32I core using TL-Verilog.This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve Hoover
RISC-V Simulator with RV32IM implementation, built during a few days off.
Neutrino is the logic core of AetherOS. It is a biological Real-Time Operating System (RTOS) developed in RUST and designed to run on bare-metal RISC-V architectures, simulated environments, or biological hardware interfaces.
An RP2350 UART driver written entirely in RISC-V Assembler.
RISCV 40 Instruction Cycle Accurate CPU Model
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