Digital Electronics course at Brno University of Technology

Example of how to get started with olofk/fusesoc.

Pipelined a real-time edge detection system with a OV7670 camera and Nexys A7 100T FPGA Trainer Board

Hardware-side component of Hastlayer for Xilinx FPGAs. See https://hastlayer.com for details.

(Your Own Digital Accelerator) A Smoothing filter by using a Finite Impulse Response (FIR) and a Low Pass Filter (LPF) algorithm. The hardware used is a NEXYS A7 Field Programmable Gate Array (FPGA) programmedin Verilog.

Real-time FPGA system integrating ToF sensing, temperature/PIR-based fan control, rotary encoder surveying, dual-buffer VGA graphics, and high-speed UART telemetry. Fully hardware-driven mapping, control, and visualization on the Nexys A7-100T.

A collection of code from a Design of Digital System and Lab class.

This accelerator uses a Nexys A7 100T FPGA to overlay an one image over another using an image mask and performing masking operations, with the results being displayed over VGA. The purpose of this project was to utilize the parallel nature of FPGAs to create a hardware accelerator for image masking applications.

End-to-end 8-bit, 5-stage pipelined CPU on Nexys A7 (Artix-7) — handwritten Verilog (RTL), MMIO-integrated embedded platform, verified bitstream.

An FPGA-based image acquisition and display system, referred to as FIADS.

Interactive memory game implemented in Verilog and deployed on Nexys-A7 FPGA using FSM-based logic.

T20 Cricket Game using Verilog coding. Includes a constraint file for implementing on Nexys A7 FPGA board.

Nexys A7 drivers for RISC-V

This is me playing around with my Nexys A7 and learning verilog. This is the Vivado project directory.

VHDL-based digital locker security system for FPGA with 3-digit hexadecimal PIN access control, seven-segment display feedback, and hardware debouncing. Supports Nexys A7 and Basys 3 boards.

A WIP RISC-V CPU implementation. Right now I'm working on implementing RV32I.

A 32-bit MIPS processor implemented in VHDL, supporting basic instructions (R, I, and J-type). Designed and simulated using ModelSim. Implements instruction fetch, decode, execute, memory access, and write-back stages.

A digital locker made for Nexys A7 using Xilinx Vivado and VHSIC Hardware Description Language

Digital Clock module created in Vivado using verilog and implementing the design on a Nexys-a7 board

A fully FPGA-based Hardware-Accelerated Parking Occupancy Management Using FPGA implemented in Verilog HDL on the Digilent Nexys A7-100T. Monitors 4 parking slots via HC-SR04 ultrasonic sensors, tracks session time, auto-calculates billing at 50 Tk/min, and reports via 7-segment display and UART serial terminal — no microcontroller involved.