Full VLSI design flow for a 1st-order IIR low-pass filter. It includes VHDL RTL, fixed-point C model, Synopsys DC synthesis with clock gating, and Cadence Innovus place & route. The advanced architecture of the filter applies J-look-ahead, pipelining, and retiming to achieve 581 MHz, a 47% throughput gain over the standard architecture.
matlab vhdl verilog digital-signal-processing pipelining vlsi questasim logic-synthesis digital-filter iir-filter retiming asic-design place-and-route rtl-design synopsys-dc hardware-design fixed-point-arithmetic cadence-innovus clock-gating nangate45
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Updated
May 4, 2026 - VHDL