Cryptographically Secure Random Number Generator (CSRNG)

System Reset Controller (sysrst_ctrl) that provides programmable hardware-level responses to trusted IOs and basic board-level reset sequencing capabilities

Entropy Distribution Network (EDN) interfaces to the CSRNG IP module

The mailbox IP block in the OpenTitan Integrated design implements a request-response channel that the host System-on-Chip (SoC) may use to request security ser

OpenTitan Rv Core Ibex IP block

This document specifies the OTP MACRO hardware IP functionality.

SRAM memory controller

Keccak Message Authentication Code (KMAC) and Secure Hashing Algorithm 3 (SHA3)

ROM controller (rom_ctrl) is the connection between the chip and its ROM

OpenTitan Flash Ctrl IP block

Analog to Digital Converter Control Interface

OpenTitan Prim Generic IP block

I2C controller

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OpenTitan Prim Xilinx Ultrascale IP block

Entropy Source: interface to an external physical random noise generator

RISC-V Debug System wrapper functionality

Always-On ("AON") Timer

OpenTitan Key Manager

Primitives - low-level reuseable components