The design of modules to reduce pipeline Hazards, as well as the MIPS processor architecture. It implements some instruction set, instruction and data memory, 32 general- purpose registers, an Arithmetic Logical Unit (ALU) for basic operation, a forwarding unit and hazards detecting unit.
mips computer-architecture hazard-detection mips-architecture mips32 nirma-university forwarding-unit control-hazards 5-stage-pipelined-processor hazard-mitigation
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Updated
Oct 27, 2024 - Verilog